Intel PCI-X manual PCI Reset Without Transition to D3, PCI Reset Sequence

Power Management

6.3.2.4PCI Reset Without Transition to D3

CLK#
	1	3
RST#			7
		4
			Memory Access Enable 8
	2
Reading EEPROM		Read EEPROM
			5
PCI Pins	Running		Running
Wakeup Enabled	Any mode		APM Wakeup
			6
PWR_STATE[1:0]	E	ELIZDNHXSLVGLVDEOHGELIZDNHXSLVHQDEOHG	EE	E
*&(,2QO\
DState	D0a	Dr	D0u	D0a

Figure 6-5. PCI Reset Sequence

Diagram #	Notes
1	In 66 MHz or PCI-Xamodes, the system must assert RST# before stopping the PCI clock. It may assert RST#
	without stopping the clock.
2	Upon assertion of RST# the Ethernet controller floats all PCI pins except PME# and goes to “Dr” state.
	In 66 MHz or PCI-X modes the system must assert RST# before stopping the PCI clock. It may assert RST#
3	without stopping the clock.
	For the 82541PI/GI/EI and 82540EP, If CLK_RUN# is enabled, then they do not require a continuous clock
	during this time, but does require that the system drive the clock in response to CLK_RUN# assertion.
4	The deassertion edge of RST# caused the EEPROM to be re-read and Wakeup disabled.
5	Synchronizing the clock circuits and circuit adjustments require up to 512 PCI clocks before the Ethernet
	controller drives PCI signals and responds to PCI transactions.
6	For the 82544GC/EI, PWR_STATE[1:0] is set to 01b if APM Wakeup is enabled, 00b otherwise.
7	The system can delay an arbitrary time before enabling memory access.

Writing a 1b to the Memory Access Enable or I/O Access Enable bit in the PCI Command Register transitions the Ethernet controller from D0u to D0 state.

8For the 82544GC/EI, writing a 1b to the Memory Access Enable or I/O Access Enable bit in the PCI Command Register transitions the Ethernet controller from D0u to D0 state and asserts both PWR_STATE outputs.

a.Not applicable to the 82541xx, 82547GI/EI, or 82540EP/EM.

136 Software Developer’s Manual