Intel PCI manual Interrupt Assignment 82547GI/EI Only, LAN Disable, Target Transaction Termination

PCI Local Bus Interface

4.4.1Target Transaction Termination

When the Ethernet controller accepts a transaction as a target it always disconnects the transaction after a single data phase by following the “Master Completion Termination” in PCI 2.2, 2.3, or “Single data phase disconnect termination” in PCI-X. The “memory” in the Ethernet controller is actually a set of registers and is marked as “non-prefetchable”. This is also the case for FLASH memory.

4.5Interrupt Assignment (82547GI/EI Only)

During a Power-On Self-Test (POST), the system BIOS must assign an Interrupt Request (IRQ) for the 82547GI(EI). The 82547GI(EI) generates an interrupt by sending a hub interface message through the CSA port.

In a typical system, the 82547GI(EI) component is Device 1 on the bus behind the CSA bridge component. When the GMCH component receives an interrupt message, it forwards the interrupt through a PIRQ programmed into the CSA Interface Interrupt Control Register (CSAINTC). Use the following information to program this register:

Address Offset - 48h

Default Value - 04h

Access - R/W

Size - 8 bits

Bit Field - [2:1]

Description - PCI Interrupt type for CSA generated Interrupt - R/W

00 - Reserved

01 - INT#B

10 - INT#C (default)

11 - INT#D

Interrupts are communicated with a special CSA bus cycle that causes the MCH to issue an interrupt to the interrupt controller in the ICH.

4.6LAN Disable

For LAN designs, it is often desirable to program the BIOS setup to selectively enable or disable LOM devices. This capability gives the end user more control over system resource management and avoids conflicts with add-in boards.

Device presence or absence must be established early during BIOS execution to ensure that resource allocation (interrupts and memory) is performed correctly. This task is frequently accomplished using a BIOS CVDR (Configuration Values Driven on Reset) mechanism.

The 82541xx and 82547GI/EI LAN disable function resides on the FLSH_SO pin. This pin should be driven by a port on the system Super IO device so that BIOS can control it dependably.

Software Developer’s Manual 91