Register Descriptions

The IODATA register can be written as a byte, word, or Dword access when the IOADDR register contains a value for the Flash (80000h - FFFFFh). In this case, the value in IOADDR must be properly aligned to the data value. Additionally, the lower 2 bits of the IODATA PCI-X access must correspond to the byte, word, or Dword access.Table 13-1lists the supported configurations:

Table 13-1. IODATA Register Configurations

 

Ethernet Controller

PCI-X1IODATA Access

PCI-X IODATA Access

Access Type

IOADDR Register Bits

AD[1:0] Bits in Address

AD C/BE#[3:0] Bits in

 

[1:0]

Phase

Data Phase

 

 

 

 

BYTE (8 bits)

00b

00b

1110b

 

 

 

 

 

01b

01b

1101b

 

 

 

 

 

10b

10b

1011b

 

 

 

 

 

11b

11b

0111b

 

 

 

 

WORD (16 bits)

00b

00b

1100b

 

 

 

 

 

10b

10b

0011b

 

 

 

 

DWORD (32 bits)

00b

00b

0000b

 

 

 

 

1.The 82540EP/EM does not support PCI-X.

Software might need to implement special code to access the Flash memory at a byte or word at a time. Example code that reads a Flash byte is shown here to illustrate the impact of Table 13-1:

char *IOADDR; char *IODATA;

IOADDR = IOBASE + 0;

IODATA = IOBASE + 4;

*(IOADDR) = Flash_Byte_Address;

Read_Data = *(IODATA + (Flash_Byte_Address % 4));

Reads to IODATA of any size returns a Dword of data. However, the chipset or CPU can only return a subset of that Dword.

For Intel architecture programmers, the IN and OUT instructions must be used to cause I/O cycles to be used on the PCI bus. Where 32-bit quantities are required on writes, the source register of the OUT instruction must be EAX (the only 32-bit register supported by the OUT command).

Writes and reads to IODATA when the IOADDR register value is in an undefined range (20000h - 7FFFCh) should not be performed. Results are indeterminate.

There are no special software timing requirements on accesses to IOADDR or IODATA. All accesses are immediate except when data is not readily available or acceptable. In this case, the Ethernet controller delays the results through normal bus methods.

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Software Developer’s Manual

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Intel PCI-X, Intel Gigabit Ethernet Controllers manual Iodata Register Configurations, AD C/BE#30 Bits