Receive and Transmit Description

The diagrams below show how the Packet Timer and Absolute Timer can be used together:

Case A: Using only an absolute timer

A bsolute Timer Value

 

PKT #1

 

PKT #2

 

 

 

 

 

 

 

 

 

PKT #3

PKT #4

Interrupt generated due to PKT #1

Case B: Using an absolute time in conjunction with the Packet timer

A bsolute Timer Value

 

PKT #1

 

PKT #2

 

PKT #3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1)Packet timer expires

2)Interrupt generated

3)Absolute timer reset

A bsolute Timer Value

PKT #4

 

PKT #5

 

PKT #6

 

...

 

...

 

...

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt generalted (due to PKT #4) as absolute timer expires.

Packet delay timer disabled untill next packet is received and transferred to host memory.

Case C: Packet timer expiring while a packet is transferred to host memory.

Illustrates that packet timer is re-started only after a packet is transferred to host memory.

A bsolute Timer Value

A bsolute Timer Value

PKT #1

 

PKT #2

 

PKT #3

 

 

 

 

 

 

 

 

 

1)Packet timer expires

2)Interrupt generated

3)Absolute timer reset

PKT #4

PKT #5

 

PKT #6

 

...

 

...

 

...

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt generalted (due to PKT #4) as absolute timer expires.

Packet delay timer disabled untill next packet is received and transferred to host memory.

3.2.7.2Small Receive Packet Detect

A Small Receive Packet Detect interrupt (ICR.SRPD) is asserted when small-packet detection is enabled (RSRPD is set with a non-zero value) and a packet of (size ≤ RSRPD.SIZE) has been transferred into the host memory. When comparing the size the headers and CRC are included (if CRC stripping is not enabled). CRC and VLAN headers are not included if they have been stripped. A receive timer interrupt cause (ICR.RXT0) is also noted when the Small Packet Detect interrupt occurs.

For the 82541xx and 82547GI/EI, receiving a small packet does not clear the absolute or packet delay timers, so one packet might generate two interrupts, one due to small packet reception and one due to timer expiration.

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Software Developer’s Manual

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Intel Intel Gigabit Ethernet Controllers, PCI-X manual Small Receive Packet Detect