Intel Intel Gigabit Ethernet Controllers Receive Small Packet Detect Interrupt1, Rsrpd 02C00h R/W

Register Descriptions

When this timer is enabled, a separate absolute countdown timer is initiated upon successfully receiving each packet to system memory. When this absolute timer expires, pending receive descriptor writebacks are flushed and a receive timer interrupt is generated.

Setting this register to 0b disables the absolute timer mechanism (the RDTR register should be used with a value of 0b to cause immediate interrupts for all receive packets).

Receive interrupts due to a Receive Packet Timer (RDTR) expiration cancels a pending RADV interrupt. If enabled, the RADV countdown timer is reloaded but halted, so as to avoid generation of a spurious second interrupt after the RDTR has been noted.

13.4.32Receive Small Packet Detect Interrupt1

RSRPD (02C00h; R/W)

31 12 11 0

Reserved

SIZE

Field	Bit(s)	Initial	Description
		Value
			If the interrupt is enabled, any receive packet of size ≤ SIZE asserts
SIZE	11:0	0b	an Interrupt. SIZE is specified in bytes and includes the headers and
			the CRC. It does not include the VLAN header in size calculation if it
			is stripped.
Reserved	31:12	X	Reserved. Reads as 0b.

13.4.33Transmit Control Register

TCTL (00400h;R/W)

This register controls all transmit functions for the Ethernet controller.

1.Not applicable to the 82544GC/EI.

306 Software Developer’s Manual