Intel PCI-X Documented MDI Register 30 Operations1, To Perform Operation MDI Read/Write Sequence

Register Descriptions

13.4.7.1.26MDI Register 30 Access Window1 R30AW (30d; R/W)

Table 13-50. MDI Register 30 Page Select Bit Description

Field	Bit(s)	Description	Mode	HW Rst	SW Rst
Register 30 Access	15:0	Provides read/write capability for	R/W	0000h	0000h
		register selected via MDI register 29.

13.4.7.1.27Documented MDI Register 30 Operations1

Unless otherwise specified, no reset operations are required in order for the following operations to take effect.

Table 13-51. MDI Register 30 Operations

To Perform	Operation	MDI Read/Write Sequence
Power down SerDes (optimize	30_31.15:0 <= x2001h	• Write MDI register 29 <= 31d
power for copper PHY operation)1		• Write MDI register 30 <= 2001h
	30_5.8 <= 0b	• Write MDI register 29 <= 5d
		• Read MDI register 30
		• Change bit 8 to 0
Tune VCO on SerDes Rx for		• Write result to MDI register 30
optimal Bit Error Ratio (BER)1	30_4.11 <= 1b	• Write MDI register 29 <= 4d
		• Read MDI register 30
		• Change bit 11 to 1
		• Write result to MDI register 30
Set PHY output drivers into Class A		• Write MDI register 29 = 11d
mode (Class AB is default after	30_11.15:0 = 8004h
		• Write MDI register 30 = 8004h
reset)

1.Not applicable to 82540EP/EM

NOTE: Any time the PHY is reset it returns to Class AB drive mode.

1.Not applicable to the 82544GC/EI, 82541xx, or 82547GI/EI.

278 Software Developer’s Manual