EEPROM Interface

5.6.26Initialization Control 3 (Word 14h1 high byte, 24h high byte)

This word controls the general initialization values.

Table 5-12. Initialization Control 3

Bit

Name

Description

 

 

 

7:5

Reserved

Reserved. Set these bits to 0b.

 

 

 

 

 

Controls the value advertised in the Interrupt Pin field of the PCI

 

 

Configuration header for this device/function.

 

 

A value of 0b (default), reflected in the Interrupt Pin field, indicates that

4

Interrupt Pin

the 82546GB/EB uses INTA#; a value of 1b indicates that the

82546GB/EB uses INTB#.

 

 

 

 

If only a single device/function of the Ethernet controller is enabled, this

 

 

value is ignored and the Interrupt Pin field of the enabled device reports

 

 

INTA# usage.

 

 

 

 

 

Set this bit to 0b (default) to enable the FLASH logic.

3

FLASH Disable

Set this bit to 1b to disable the FLASH logic. Note that the Expansion

ROM & secondary FLASH access BARs in PCI configuration space are

 

 

 

 

also disabled.

 

 

 

 

 

Initial value of Advanced Power Management Wakeup Enable in the

2

APM Enable

Wakeup Control Register (WUC.APME).

 

 

The default for this bit is 0b.

 

 

 

 

 

Initial value of Link Mode bits of the Extended Device Control Register

 

 

(CTRL_EXT.LINK_MODE), specifying which link interface and protocol

 

 

is used by the MAC.

 

 

For Address 24h (High Byte) / LAN A

 

 

00b = MAC operates in GMII/MII mode with internal copper PHYa

 

 

01b = External GMII/MII mode

1:0

Link Mode

10b = Internal SerDes mode (not applicable to the 82540EP/EM)

 

 

11b = MAC operates in TBI mode using external TBI interface

 

 

For Address 14h (High Byte) / LAN B

 

 

00b = MAC operates in GMII/MII mode with internal copper PHY

 

 

01b = Reserved

 

 

10b = Internal SerDes mode (not applicable to the 82540EP/EM)

 

 

11b = MAC operates in TBI mode using external TBI interface

 

 

 

a.For the 82540EP/EM, 82541PI/GI/EI, and 82547GI/EI to properly communicate with the internal copper PHY, this value must be set to 00b.

Note: Since the 82546GB/EB is a dual-port device, the Initialization Control Word 3 bit assignments are port specific.

1.Applicable to the 82546GB/EB only.

Software Developer’s Manual

115

Page 129
Image 129
Intel PCI-X manual Initialization Control 3 Word 14h1 high byte, 24h high byte, 82546GB/EB uses INTB#