Intel PCI-X, Intel Gigabit Ethernet Controllers manual Preen, Sfd

Register Descriptions

Table 13-32. PHY Port Configuration Register Bit Description

Field	Bit(s)		Description	Mode	HW Rst	SW Rst
		Auto_MDIX Parallel Detect Bypass.
		Bypasses the fix to IEEE auto-MDIX
		algorithm for the case where the PHY is
		in forced-speed mode and the link
		partner is auto-negotiating.
Auto MDIX Parallel	4	1b = Strict 802.3 Auto-MDIX algorithm.		R/W	0b	0b
Detect Bypass		0b = Auto-MDIX algorithm handles
		Auto-Negotiation disabled modes. This
		is accomplished by lengthening the
		auto-MDIX switch timer before
		attempting to swap pairs on the first time
		out.
		Preamble Enable
PRE_EN	5	0b	= Set RX_DV high coincident with	R/W	1b	1b
		SFD.
		1b	= Set RX_DV high and RXD =
		preamble (after CRS is asserted).
Reserved	6	Write to 0b for normal operation.		R/W	0b	0b
Smart Speed	7	1b	= Smart Speed selection enabled.	R/W	0b	0b1
		0b	= Smart Speed selection disabled.
TP Loopback		1b	= Disable TP loopback during half-
	8	duplex operation.		R/W	1b	1b
(10BASE-T)
		0b	= Normal operation.
Reserved	9	Write to 0b for normal operation.		R/W	0b	0b
Jabber (10BASE-T)	10	1b	= Disable jabber.	R/W	0b	0b
		0b	= Enable jabber.
Bypass 4B5B		1b	= Bypass4B5B encoder and
	11	decoder.		R/W	0b	0b
(100BASE-TX)
		0b	= Normal operation.
Bypass Scramble		1b	= Bypass scrambler and
	12	descrambler.		R/W	0b	0b
(100BASE-TX)
		0b	= Normal operation.
Transmit Disable	13	1b	= Disable twisted-pair transmitter.	R/W	0b	0b
		0b	= Normal operation.
		1b	= Force link pass
		0b	= Normal operation
		For 10BASE-T, this bit forces the link
		signals to be active. In 100BASE-T
Link Disable	14	mode, setting this bit should force the		R/W	0b	0b
		Link Monitor into it’s LINKGOOD state.
		For Gigabit operation, this merely
		bypasses Auto-Negotiation—the link
		signals still correctly indicate the
		appropriate status.
Reserved	16:15	Always read as 0b. Write 0b for normal		R/W	0b	0b
		operation.

1.The default for this bit is determined by EEPROM bit SSPEED.

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