Rxcw Register Bit Description, 82544GC/EI only | Intel PCI-X

Register Descriptions

Table 13-59. RXCW Register Bit Description

	Field	Bit(s)	Initial	Description
	Field	Bit(s)	Value	Description
			Value

				Data received during Auto-Negotiation process.
				When performing hardware Auto-Negotiation
				(TXCW.ANE = 1b), the “AN link partner ability base page
	RxConfigWord	15:0	X	register” is recorded in the RxConfigWord.
	RxConfigWord	15:0	X	When TXCW.ANE is clear, then this register is used by
				When TXCW.ANE is clear, then this register is used by
				software to perform software based Auto-Negotiation. In
				that capacity, RxConfigWord records the raw values
				returned from the Auto-Negotiation process.

				Reserved
	Reserved	25:16	0b	Reads as 0b.
				Should be written with 0b for future compatibility.

				Carrier Sense Indication
				0b = Ethernet controller not receiving idle characters
				(Carrier sense is true)
				1b = Ethernet controller receiving idle characters (Carrier
				sense is false)
				Hardware sets RxConfigNoCarrier when it is receiving idle
	RxConfigNoCarrier	26	0b	characters (and when receiving link configuration
				information or port status).
				Software can use this bit to determine that idles have been
				seen prior to exiting the link start-up procedure.
				82544GC/EI only:
				Valid only in software Auto-Negotiation mode
				(TXCW.ANE = 0b).

				Invalid Symbol during configuration process
				0b = Have not received an invalid symbol during Auto-
				Negotiation process.
				1b = Have received an invalid symbol during Auto-
				Negotiation process (bit is LH).
				If the Ethernet controller detects an invalid symbol at any
	RxConfigInvalid	27	0b	time, it sets the RxConfigInvalid bit. The bit is latched high
	RxConfigInvalid	27	0b	until read by software. Software is expected to restart the
				until read by software. Software is expected to restart the
				configuration process when the Ethernet controller receives
				an invalid symbol at any time during the Auto-Negotiation
				process.
				82544GC/EI only:
				Valid only in software Auto-Negotiation mode
				(TXCW.ANE = 0b).

				Change to the RxConfigWord indication
				0b = RxConfigWord has changed since last read.
				1b = RxConfig is unchanged since last read (LH)
	RxConfigChange	28	0b	Indicates that the Ethernet controller interface has seen a
	RxConfigChange	28	0b	change to the RxConfigWord. This bit is latched high until
				read by software.
				82544GC/EI only:
				Valid only in software Auto-Negotiation mode
				(TXCW.ANE = 0b).

284	Software Developer’s Manual

Image 298

Intel PCI-X, Intel Gigabit Ethernet Controllers manual Rxcw Register Bit Description, 82544GC/EI only

Contents

82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, Software Developer’s Manual Date Version Comments Initial Public Release Software Developer’s Manual Contents TCP Segmentation Use of Multiple Data Descriptors Software Developer’s Manual Vii Power Management 129 Introduction to Power Management 10.1.3 203 13.4.25 13.7.10 Appendix 82540EP/EM and 82545GM/EM Differences Xiv Scope Overview CSA Features 82547GI/EI Only Ethernet Controller FeaturesPCI Features Network Side Features Host Offloading Features Additional Performance Features Additional Ethernet Controller Features Technology Features Memory Alignment Terminology ConventionsRelated Documents Register and Bit References Architectural Overview Introduction PHY External ArchitectureLAN a LAN B ECHO, Next Fext Eeprom FlashAGC, A/D Microarchitecture 1 PCI/PCI-X Core Interface 2 82547GI/EI CSA Interface DMA Engine and Data Fifo 4 10/100/1000 Mb/s Receive and Transmit MAC Blocks 5 MII/GMII/TBI/Internal SerDes Interface Block 6 10/100/1000 Ethernet Transceiver PHY Eeprom Interface Example 2-1. Byte Ordering DMA AddressingFlash Memory Interface Little Endian Data Ordering Intel Architecture Byte Ordering Ethernet AddressingIA Byte # LSB MSB Interrupts Checksum Offloading Hardware Acceleration CapabilityBuffer and Descriptor Structure TCP Segmentation Architectural Overview Packet Reception IntroductionPacket Address Filtering Receive Descriptor Format Receive Data StorageReceive Descriptor Rdesc Layout PIF Ipcs Tcpcs RSV Ixsm EOP Receive Descriptor Status FieldReceive Status RDESC.STATUS Layout Receive Receive Descriptor Errors Field RSV SEQ Receive Errors RDESC.ERRORS LayoutRXE IPE Tcpe RSV CXE PRI CFI Vlan Receive Descriptor Special FieldSpecial Descriptor Field Layout PRI Receive Descriptor Fetching Receive Descriptor Fetching Algorithm Receive Descriptor Packing Receive Descriptor Write-BackReceive Descriptor Queue Structure Null Descriptor Padding Receive Descriptor Ring Structure Receive Interrupt Delay Timer / Packet Timer Rdtr Receive Timer InterruptReceive Interrupts Receive Interrupt Absolute Delay Timer Radv Packet Delay Timer Operation State Diagram Small Receive Packet Detect Receive Descriptor Minimum Threshold ICR.RXDMT 8 82544GC/EI Receive InterruptsReceive Packet Checksum Offloading Receiver Fifo Overrun Supported Receive Checksum Capabilities Packet Type HW IP Checksum HW TCP/UDP Checksum Calculation Packet Type HW IP Checksum HW TCP/UDP Checksum MAC Address FilterGC/EI Supported Receive Checksum Capabilities Packet Type HW IP Checksum 9.3 IPv4 Filter Packet TransmissionSNAP/VLAN Filter 9.4 IPv6 Filter Transmit Data Storage Transmit Descriptors Transmit Descriptor Tdesc Layout Transmit Descriptor Tdesc Layout Legacy ModeLegacy Transmit Descriptor Format Transmit Descriptor Legacy Descriptions STA Transmit Descriptor Description LegacyCMD CSS IDE VLE Dext RSV Transmit Descriptor Command Field Format10. Transmit Command TDESC.CMD Layout Ifcs EOP Transmit Descriptor Status Field Format 11. Transmit Status Layout Transmit Descriptor Special Field Format 12. Special Field TDESC.SPECIAL Layout 5 TCP/IP Context Transmit Descriptor Format 6 TCP/IP Context Descriptor Layout 13. Transmit Descriptor Tdesc Layout Type = 0000b 14. Transmit Descriptor Tdesc Layout Transmit Description Descriptor Offload Tucmd 6.1 TCP/UDP Offload Transmit Descriptor Command FieldTransmit Description Dtyp IDE RSV Dext TSE TCP 15. Command Field TDESC.TUCMD Layout82544GC/EI only 6.2 TCP/UDP Offload Transmit Descriptor Status Field 7 TCP/IP Data Descriptor Format16. Transmit Status Layout Popts RSV STA Dcmd Dtyp Dtalen 17. Transmit Descriptor Tdesc Layout Type = 0001bPopts IDE VLE Dext 7.1 TCP/IP Data Descriptor Command Field18. Command Field TDESC.DCMD Layout TSE Ifcs EOP 19. Transmit Status Layout 7.2 TCP/IP Data Descriptor Status FieldReserved 20. Packet Options Field TDESC.POPTS Layout 7.3 TCP/IP Data Descriptor Option Field7.4 TCP/IP Data Descriptor Special Field RSV Txsm Ixsm Transmit Descriptor Ring Structure 21. Special Field TDESC.SPECIAL Layout Transmit Descriptor Ring Structure Transmit Descriptor Fetching Transmit Descriptor Write-back Transmit Interrupts Delayed Transmit Interrupts Assumptions Transmission Process TCP Segmentation Data Fetch Control TCP Segmentation PerformancePacket Format TCP/UDP Data FCS TCP Segmentation Indication 3936 TCP Segmentation Use of Multiple Data Descriptors TCP Partial Pseudo-Header Checksum Version IP Hdr IP and TCP/UDP HeadersOptions Fragment Offset Low Type of service Version IP Hdr Length FragmentOffset High Header Checksum Length Checksum Urgent Pointer Options Destination Port Sequence NumberTCP Header Byte1 Byte0 Destination Port Source Port Destination Port Length Checksum Byte3 Byte2 Byte1 Byte0 17. UDP Pseudo Header Diagram for IPv4 Transmit Checksum Offloading with TCP Segmentation 9 IP/TCP/UDP Header Updating 19. Overall Data Flow 9.1 TCP/IP/UDP Header for the First Frame 9.2 TCP/IP/UDP Header for the Subsequent Frames IP/TCP/UDP Transmit Checksum Offloading 9.3 TCP/IP/UDP Header for the Last Frame Ipcss Receive and Transmit Description Address Description PCI ConfigurationMandatory PCI Registers PCI Specification Update for the latest stepping information Base Address Registers Addr All base address registers have the following fields Field Bits Read Initial Description Write Value Expansion ROM Base Address Offset Space Capabilities Linked List Address Next Pointer PCI definition for more details Bits Initial Value Description Status Register Layout 82547GI/EI Next Capability PCI-X Configuration RegistersPCI-X Capability ID Byte Offset Write Value PCI-X CommandBits Read Initial Maximum Memory Read Byte Count. This register sets USC SCD PCI-X StatusBits Read Intial Description Write Value Command Register as follows Reserved and Undefined Addresses MSI Capability ID Message Signaled Interrupts1Message Signaled Interrupt Configuration Registers Bits Read Initial Description Write Value 05h Message Control 3.1.5 Message Upper Address Commands3.1.4 Message Address 3.1.6 Transaction Target PCI Commands PCI-X Commands Accepted PCI/PCI-X Command as a TargetPCI Commands Abr PCI-X Commands Transaction Cause PCI Commands PCI-X Commands PCI/PCI-X Command Usage Memory Write Operations Master Write Command Usage Algorithm MWI Bursts MW Bursts PCI-X Command UsageMemory Read Operations Rules for Memory Read Operations Cache Line Information1 Outstanding Memory Read Interrupt Assignment 82547GI/EI Only LAN DisableTarget Transaction Termination CardBus Application 82541PI/GI/EI Only Eeprom Interface General Overview Component Identification Component Identification Via Programming InterfaceStepping Vendor ID Device ID Description Eeprom Device and Interface Software Access Signature and CRC Fields Eeupdate Utility Command Line Parameters Word Used Bit Image Eeprom Address Map1Ethernet Controller Address Map For the 82541xx and 82547GI 82541xx and 82547GI/EI only LAN a82545GM 82540EP 82546GB/EB only 82541xx 82545GM 82540EP/EM ASF GC/EI and 82541ER Eeprom Address Map Word Description Default HW AccessAddress Hi Byte Low Byte Software Compatibility Word Word 03h Ethernet Address Words 00h-02hSoftware Compatibility Word Word 03h Bit Name Description Compatibility Fields Word 05h 07h SerDes Configuration Word 04hEeprom Image Version Word 05h PBA Number Word 08h, 09h Initialization Control Word 1 Word 0Ah Initialization Control Word 1 Word 0Ah Subsystem ID Word 0Bh Subsystem Vendor ID Word 0Ch Initialization Control Word 2 Word 0Fh Device ID Word 0Dh, 11h1Vendor ID Word 0Eh Initialization Control Word 2 Word 0Fh 82541PI/GI Only PHY Register Address Data Words 10h, 11h, and 13h 1Eh Common Power Word 12hSoftware Defined Pins Control Word 10h1, 20h OEM Reserved Words Words 10h, 11h, 13h 1Fh Software Defined Pins Control Word 10h, 20h CSA Port Configuration 2 Word 21h CSA Port Configuration 2 Word 21hBit Description Default Circuit Control Word 21h 20 D0 Power Word 22h high byte21 D3 Power Word 22h low byte Reserved Words 23h 2Eh Management Control Word 13h1, 23h2 10. Initial Management Control Register Settings82541PI/GI/EI and 82547GI/EI Only SMBus Slave Address Word 14h1 low byte, 24h low byte 11. SMBus Slave Address 82546GB/EB uses INTB# Initialization Control 3 Word 14h1 high byte, 24h high byte12. Initialization Control For Address 24h High Byte / LAN a 27 IPv4 Address Words 15h 16h1 and 25h 26h LED Configuration Defaults Word 2Fh2Boot Agent Main Setup Options Word 30h 28 IPv6 Address words 17h 1Eh1 and 27h 2Eh 15. Boot Agent Main Setup Options DBS Boot Agent Configuration Customization Options Word 31hBBS Mode 16. Boot Agent Configuration Customization Options Word 31hSIG DFU Boot Agent Configuration Customization Options Word 32h 17. Boot Agent Configuration Customization Options Word 32h IBA Capabilities Word 33h IBA Secondary Port Configuration Words 34h-35h18. IBA Capabilities Checksum Word Calculation Word 3Fh 19. WOL Mode and Functionality Word 0Ah20. WOL Mode and Functionality Word 20h Eeprom Images Manufacturer Parallel Flash Memory21. Flash Memory Manufacturers Number 124 Flash Control and Accesses Flash Interface Operation Read Accesses Write Accesses Flash Buffer Write Cycle 128 Introduction to Power Management Assumptions Power States D3cold support Dr State 1.2 D0u State 1.3 D0a D0 active Timing1.4 D3 Power Up Off to Dr to D0u to D0a Diagram # Transition From D0a to D3 and Back Without PCI Reset Transition from D0a to D3 and Back Without PCI Reset Transition From D0a to D3 and Back with PCI Reset RST# PCI Reset Without Transition to D3 PCI Reset Sequence Capability ID Byte Offset = 0 RO PCI Power Management RegistersBits Default Description Next Item Pointer Byte Offset = 1 RO Reserved Power Management Capabilities PMC 2 Bytes Offset = 2 ROEeprom Software Developer’s Manual 139 Byte Offset = 6 RO Pmcsrbse Bridge Support Extensions3.6 Data Register Byte Offset = 7 RO Advanced Power Management Wakeup Wakeup Acpi Power Management Wakeup Pre-Defined Filters Wakeup PacketsDirected Exact Packet 3.1.4 Magic Packet*1 3.1.3 BroadcastDirected Multicast Packet Offset Field Value Action Comment Offset Field Value Action Comment Bytes + D + S a 3.1.5 ARP/IPv4 Request Packet1+ S a ARP Directed IPv4 Packet1 Offset # of bytes Field Value Action Comment Directed IPv6 Packet1 + S IPX Diagnostic Responder Request Packet Example1Flexible Filter + D + S Directed IPX Packet Example 3.4 IPv6 Neighbor Discovery Filter1 Wakeup Packet Storage CRC 152 Ethernet Interface Link Interfaces Overview Internal SerDes Interface/TBI Mode- 1Gb/s1 1.2 8B10B Encoding/Decoding Code Group and Ordered Set Usage Gmii 1 Gb/sCode Groups and Ordered Sets Code OrderedSet Duplex Operation Internal Interface1MII 10/100 Mb/s Full Duplex Half Duplex Carrier Extension 1000 Mb/s Only Packet Bursting Auto-Negotiation and Link Setup1 Auto-Negotiation and Link Setup2 Link Speed Link Configuration in Internal Serdes/TBI Mode1Auto-Negotiation TXCW.txConfigWord Hardware Auto-Negotiation Software Auto-Negotiation Bit Description Internal GMII/MII Mode Forcing Link Using Auto-Speed Detection ASD Forcing Speed MII Management Registers Automatic Detection of Link Speed using SPD-INDDuplex Comments Regarding Forcing Link Internal Serdes1 Mode Software Enabled Internal SerDes Mode1 Control Bit ResolutionInternal Serdes Mode1 Hardware Enabled Control Bit Effect on Control Bits GMII/MII Mode PHY Speed Indication Internal PHY Mode Control Bit ResolutionInternal Serdes Mode1 Auto-Negotiation Skipped GMII/MII Mode Auto-Speed Detection GMII/MII Mode Force Speed Internal PHY Mode Loss of Signal/Link Status IndicationInternal Serdes Mode GMII/MII Mode Force Link 10/100 Mb/s Specific Performance Enhancements Adaptive IFS1 10. Flow Control Registers Flow ControlMAC Control Frames & Reception of Flow Control Packets Register Name Description 3x MAC Control Frame Format Discard Pause Frames and Pass MAC Control Frames Transmission of Pause Frames Software Initiated Pause Frame Transmission External Control of Flow Control Operation1 Vlan Packet Format Comparison 802.1q Vlan Packet Format1 802.1q Tagged Frames Packet #Octets Adding 802.1q Tags on Transmits Transmitting and Receiving 802.1q Packets802.1q Vlan Packet Filtering Stripping 802.1q Tags on Receives Packet Reception Decision Table VFE 178 Configurable LED Outputs1 Selecting an LED Output Source Polarity Inversion Blink Control Blink Control 182 PHY Functionality and Features Auto-Negotiation Register Update Next Page Exchanges Pin 11.2 MDI/MDI-X Crossover copper onlyStatus 1000BASE-T Polarity Correction copper only 11.2.2 10/100 Downshift 82540EP/EM Only Cable Length Detection copper only PHY Power Management copper onlyLink Down Energy Detect copper only 11.4.4 D3 Link-Up, Speed-Management Disabled copper only 11.4.3 D3 Link-Up, Speed-Management Enabled copper only11.4.2 D3 State, No Link Required copper only Mdio Control Mode Initialization Determining Link State Overview of Link Establishment Forced Operation Configuration ResultFalse Link Determining Duplex State Via Parallel Detection Parallel Detection Link CriteriaAuto Negotiation 11.7.1 1000BASE-T 11.7.3 10BASE-T Using SmartSpeedLink Enhancements SmartSpeed Asmdir Settings Pause Setting Low Power OperationPause And Asymmetric Pause Settings Management Data Interface Smart Power-Down Powerdown via the PHY Register11.11 1000 Mbps Operation DSP ECHO, Next 4DPAM5 Transmit Functions Transmit Fifo Line Driver Spectral ShaperLow-Pass Filter Transmit/Receive Flow Receive Functions Descrambler 11.12 100 Mbps Operation11.13 10 Mbps Operation Viterbi Decoder/Decision Feedback Equalizer DFE PHY Line Length Indication 202 Introduction1 Features of Each MAC12.2.1 PCI/PCI-X interface 204 12.2.3 SDP, LED, INT# output MAC Configuration Register SpaceIO BAR Eeprom Map Shared EepromEeprom Arbitration Flash Access Contention Shared Flash Values Sampled on Reset Pin sampled LAN device controlled Enable/Disable Multi-Function Advertisement Power ReportingInterrupt Use Interrupt Line Used EnabledSummary INTA# Register Descriptions Register Conventions Memory-Mapped Access to Expansion ROM Memory-Mapped Access to Internal Registers and MemoriesMemory-Mapped Access to Flash Memory and I/O Address Decoding Offset Abbreviation Name Size IoaddrIodata Ioaddr Iodata Register Configurations AD C/BE#30 Bits 82544GC/EI Ethernet Controller Register SummaryCategory Offset Abbreviation Name 82547GI/EI only Ipat 82544GC PRC64 XofftxcFcruc Gprc 82544GC/EI , 82541xx , or 82547GI/EI CategoryAbbreviation Name Register To the 82544GC/EI , 82541xx , or 82547GI PCI-X Register Access Split1 Device Control Register Main Register DescriptionsCtrl 00000h R/W Ctrl Register Bit Description Field Bits Initial Description Value Ilos SLUSpeed SDP1DATA FrcdplxSDP0DATA ADVD3WUC Field Bits Initial Description Status 00008h R BEM = 0 64-bit mode Little-EndianDevice Status Register Little-Endian Data Ordering Txoff Status Register Bit DescriptionTbimode Pcixmode AsdvPCI66 Pcixspd Eecd Register Bit Description EEPROM/Flash Control & Data RegisterEecd 00010h R/W 82544GC/EI Only Eepres EereqEegnt Eesize Eerd 00014h RW Eeprom Read Register1Eeprom Read Register Bit Description Eeprom Read Register Bit Description 82541xx and 82547GI/EI Done Start Flash Access FLA Flash Access1FLA 0001Ch R/W 10. Ctrlext Register Bit Description Extended Device Control RegisterCtrlext 00018h, R/W 23 16 SDP7IODIR SDP6IODIRSDP2IODIR Asdchk Down Vreg Power11. GPI to SDP Bit Mappings Linkmode Swdpiohi Swdpinshi12 GC/EI Ctrlext Register Bit Description CTRL.RST 13 GC/EI GPI to SDP Bit Mapping MDI Control Register Mdic 00020h R/W Regadd 14. MDI Control Register Bit DescriptionRSV PHY REG Data Phyadd Register Mode Description 15. PHY Register Bit Mode DefinitionsPHY Registers Field Bits Description Mode HW Rst SW Rst MSB 242 Enaxc LSB RO,L Software Developer’s Manual 245 246 For the 82541xx and 82547GI/EI 82544GC/EI only 82541xx Pause 82541xx 82547GI/EI 82541xx and 82547GI/EI only ANEG2 82544GC/EI OnlyANEG3 RF1 Software Developer’s Manual 251 23. Link Partner Ability Register Base Page Bit Description1 10BASE-T 82541xx and 82547GI/EI Only24. PHY Link Page Ability Bit Description1 100BASE-TX 1b 82541xx Software Developer’s Manual 255 Bits Field Description Mode HW Rst SW Rst MASTER/SLAVE MasterANEG0 ANEG1 258 Software Developer’s Manual 259 DIS NLP Preen SFD Software Developer’s Manual 263 264 Software Developer’s Manual 265 266 82541EI/82547GI B0 stepping 82541/GI/ER and 82547GI B1 268 HCD NOK Software Developer’s Manual 271 272 Field Bits Description Mode HW Rst Ledactled SPEED100LED SPEED1000LED 276 Software Developer’s Manual 277 51. MDI Register 30 Operations Documented MDI Register 30 Operations1To Perform Operation MDI Read/Write Sequence Fcal 00028h R/W Flow Control Address LowFlow Control Address High Fcah 0002Ch R/W FCT 00030h R/W Flow Control TypeVlan Ether Type VET 00038h R/W 56. VET Register Bit Description Flow Control Transmit Timer ValueFcttv 00170h R/W 57. Fcttv Register Bit Description Txcw 00178h R/W Transmit Configuration Word Register158. Txcw Register Bit Description Receive Configuration Word Register1 Rxcw 00180h R 59. Rxcw Register Bit Description ANC LED Control1Ledctl 00E00h RW LED1 ACTIVITY# LED0 LINKUP# Mode Encodings for LED Outputs1 60. LED Control Bit Description1 61. Mode Encodings for LED Outputs Mode Pneumonic State / Event Indicated 62. PBA Register Bit Description Packet Buffer AllocationPBA 01000H R/W Field Bits Initial Value Description ICR 000C0H R Interrupt Cause Read Register63. ICR Register Bit Description Rxcfg RXT0Mdac GPISDP6 ITR 000C4h R/W Interrupt Throttling Register1Interval ICS 000C8h W Interrupt Cause Set Register64. ICS Register Bit Description 65. IMS Register Bit Description Interrupt Mask Set/Read RegisterIMS 000D0h R/W To the 82544GC/EI Interrupt Mask Clear Register IMC 000D8h W 66. IMC Register Bit Description 67. Rctl Register Bit Description Receive Control RegisterRctl 00100h R/W SBP LBM MPELPE Rdmts VFE BAMBsize Cfien Bsex PmcfSecrc Fcrtl 02160h R/W XON Enable 82544GC/EI , 82541xx , and 82547GI/EI onlyFlow Control Receive Threshold Low 68. Fcrtl Register Bit Description Fcrth 02168h R/W Flow Control Receive Threshold High69. Fcrth Register Bit Description Rdbal 02800hR/W Receive Descriptor Base Address LowReceive Descriptor Base Address High Rdbah 02804h R/W Rdlen 02808h R/W Receive Descriptor LengthReceive Descriptor Head RDH 02810h R/W RDT 02818hR/W Receive Delay Timer RegisterReceive Descriptor Tail Rdtr 02820h R/W Receive Interrupt Absolute Delay Timer1 Radv 0282Ch RW Rsrpd 02C00h R/W Receive Small Packet Detect Interrupt1Transmit Control Register Tctl 00400hR/W PSP 76. Tctl Register Bit DescriptionCold TCTL.COLD Rtlc Transmit IPG RegisterTipg 00410R/W Nrtu 77. Tipg Register Bit Description IPGR2 IPGR1 Ipgt Aifs 00458R/W Adaptive IFS Throttle AITIPGR2 78. Aifs Register Bit Description Transmit Descriptor Base Address LowTdbal 03800h R/W 79. Tdbal Register Bit Description Tdbah 03804h R/W Transmit Descriptor Base Address HighTransmit Descriptor Length Tdlen 03808h R/W TDH 03810h R/W Transmit Descriptor Head82. TDH Register Bit Description TDT 03818h R/W Transmit Interrupt Delay ValueTransmit Descriptor Tail Tidv 03820h R/W Txdmac 03000h R/W TX DMA Control 82544GC/EI onlyTransmit Descriptor Control Txdctl 03828h R/W 86. Txdctl Register Bit Description Lwthresh RSV1 Gran RSV Wthresh Hthresh Pthresh Gran Transmit Absolute Interrupt Delay Value1Tadv 0382Ch RW Lwthresh Tspbp Tsmt TCP Segmentation Pad And Minimum Threshold Tspmt 03830h RWTspbp Software Developer’s Manual 319 87. Rxdctl Register Bit Description Receive Descriptor ControlRxdctl 02828h R/W Wthresh RSV Hthresh Pthresh 88. Rxcsum Register Bit Description Receive Checksum ControlRxcsum 05000h R/W 3111 Tuofld IpofldIPV6OFL MTA1270 05200h-053FCh R/W Filter RegistersMulticast Table Array 89. MTA Register Bit Description Destination Address RAL 05400h + 8*n R/W Receive Address LowReceive Address High RAH 05404h + 8∗n R/W 91. RAH Register Bit Description Vlan Filter Table Array1VFTA1270 05600h 057FCh R/W RAH WUC 05800h R/W Wakeup RegistersWakeup Control Register 92. VFTA1270 Bit Description Apmpme Wakeup Filter Control RegisterWufc 05808h R/W SPM Wakeup Status Register WUS 05810h R 330 IP Address Valid Ipav 5838h R/W Address 13.6.5 IPv4 AddressIP4AT 05840h 05858h R/W2 Field Dword # Address Bits Initial Value Description IPV6ADDR0 13.6.6 IPv6 AddressIP6AT 05880h 0588Ch R/W Dword # Address Bits Initial Value Description Wakeup Packet Memory 128 Bytes Wakeup Packet LengthFlexible Filter Length Table LEN1 Flexible Filter Mask Table Ffmt 09000h 093F8h R/WLEN0 LEN2 Flexible Filter Value Table Statistics RegistersFfvt 09800h 09BF8h R/W Crcerrs 04000h R CRC Error CountAlignment Error Count Algnerrc 04004h R Symerrs 04008h R Symbol Error CountRX Error Count Rxerrc 0400Ch R MPC 04010h R Missed Packets CountSingle Collision Count SCC 04014h R Ecol 04018h R Excessive Collisions CountMultiple Collision Count MCC 0401Ch R Latecol 04020h R Late Collisions CountCollision Count Colc 04028h R DC 04030h R Defer CountTransmit with No CRS Tncrs 04034h R SEC 04038h R Sequence Error CountCarrier Extension Error Count Cexterr 0403Ch R Rlec 04040h R Receive Length Error CountXON Received Count Xonrxc 04048h R Xoff Received Count XON Transmitted CountXoff Transmitted Count Fcruc 04058h R FC Received Unsupported CountPackets Received 64 Bytes Count PRC64 0405Ch R PRC127 04060h R Packets Received 65-127 Bytes CountPackets Received 128-255 Bytes Count PRC255 04064h R PRC511 04068h R Packets Received 256-511 Bytes CountPackets Received 512-1023 Bytes Count PRC1023 0406Ch R PRC1522 04070h R Packets Received 1024 to Max Bytes CountGood Packets Received Count Gprc 04074h R Bprc 04078h R Broadcast Packets Received CountMulticast Packets Received Count Mprc 0407Ch R Gptc 04080h R Good Packets Transmitted CountGood Octets Received Count Gorcl 04088h R/GORCH 0408Ch R Gotcl 04090h R/ Gotch 04094 R Good Octets Transmitted CountReceive No Buffers Count Rnbc 040A0h R RUC 040A4h R Receive Undersize CountReceive Fragment Count RFC 040A8h R ROC 040ACh R Receive Oversize CountReceive Jabber Count RJC 040B0h R Mgtprc 040B4h R Management Packets Received Count1129. RJC Register Bit Description Management Pkts Transmitted Count1 Management Packets Dropped Count1Total Octets Received 130. Torl and Torh Register Bit Descriptions Total Octets TransmittedTotl 040C8h R/W / Toth 040CCh R 131. Totl and Toth Register Bit Descriptions TPR 040D0h R Total Packets ReceivedTotal Packets Transmitted TPT 040D4h R PTC64 040D8h R Packets Transmitted 64 Bytes CountPackets Transmitted 65-127 Bytes Count PTC127 040DCh R PTC255 040E0h R Packets Transmitted 128-255 Bytes CountPackets Transmitted 256-511 Bytes Count PTC511 040E4h R PTC1023 040E8h R Packets Transmitted 512-1023 Bytes CountPackets Transmitted 1024 Bytes or Greater Count PTC1522 040ECh R Mptc 040F0h R Multicast Packets Transmitted CountBroadcast Packets Transmitted Count Bptc 040F4h R Tsctc 040F8h R TCP Segmentation Context Transmitted CountTCP Segmentation Context Transmit Fail Count Tsctfc 040FCh R Receive Data Fifo Tail Register Diagnostics RegistersReceive Data Fifo Head Register Rdfh 02410h R/W Rdfhs 02420h R/W Receive Data Fifo Head Saved RegisterReceive Data Fifo Tail Saved Register Rdfts 02428h R/W Rdfpc 02430h R/W Receive Data Fifo Packet CountTransmit Data Fifo Head Register Tdfh 03410h R/W Tdft 03418h R/W Transmit Data Fifo Tail RegisterTransmit Data Fifo Head Saved Register Tdfhs 03420h R/W Tdfts 03428h R/W Transmit Data Fifo Tail Saved RegisterTransmit Data Fifo Packet Count Tdfpc 03430h R/W 151. Tdfpc Register Bit Description Packet Buffer MemoryPBM 10000h 1FFFCh R/W 152. PBM Bit Description 370 Power Up State General Configuration General Initialization and Reset Operation Receive Initialization Transmit Initialization Fiber Copper 82544GC/EI Ipgt IPGR1 IPGR2 Signal Descriptions Signal Ball Name and Function Receive Data Signal InterfaceCarrier Sense Receive Clock Signal Function Pin Gmii 1000 Mbps Operations GMII/MII Features not SupportedSignal Functions MII 10/100 Mbps Differences Signal Functions Not Supported Avoiding Gmii Test Modes MAC ConfigurationDirect PHY Indications to MAC Link Setup CTRL.FD PHY Initialization 10/100/1000 Mb/s Copper Media CTRL.RFCE Reset Operation Lanpwrgood 382 Software Developer’s Manual 383 Initialization of Statistics Fifo Data DiagnosticsFifo State Loopback Testability Internal Loopback Idcode Instruction Extest InstructionSAMPLE/PRELOAD Instruction Bypass Instruction 388 New Features Appendix Changes From 82544EI/82544GC Register Offset Register ChangesTable A-1. Register Changes EEC 82540EP/EM Differences Serial Flash Interface Single-Port Functionality No TBI/Internal SerDes Interface4 32-Bit PCI Support