Intel Intel Gigabit Ethernet Controllers, PCI-X manual 276

Register Descriptions

Table 13-45. SPEED_100_LED and SPEED_1000_LED Bit Description

		Disable the SPEED_1000_LED
		Extension Logic.
		0b = Enable logic.
LED Stretch Disable	11	1b = Disable logic.	R/W	1b	1b
		Note: Only when both the stretch and
		blink are disabled the input bypasses
		the blink logic and is muxed out with no
		sampling (only combinational logic).
Reserved	15:12	Always read as 0b. Write to 0b for	R/W	00b	00b
		normal operation

13.4.7.1.22PHY LED Control Register (82544GC/EI Only) PLED (24d; R/W)

Table 13-46. PHY LED Control Bit Description

Field	Bit(s)			Description	Mode	HW Rst	SW Rst
LED_TX control	0	1b	= Activity/Link.		R/W	0b	Retain
		0b	= Transmit activity.
LED_RX control	1	1b	= Receive activity/Link.		R/W	0b	Retain
		0b	= Receive activity.
Reserved	2	Reserved. Should be set to 0b.			R/W	0b	Retain
		1xb = Link[2:1], Link.
LED_LINK control	4:3	01b = Link, Speed[1:0].			R/W	00b	Retain
		00b = Link[2:0].
Reserved	7:5	Reserved. Should be set to 000b.			R/W	000b	Retain
		000b		= 42 ms.
		001b		= 84 ms.
Blink Rate	10:8	010b		= 170 ms.	R/W	001b	Retain
		011b = 340 ms.
		100b		= 670 ms.
		101b to 111b = Reserved.
Force INT# to Assert	11	0b	= Do not force INT# assertion.		R/W	0b	Retain
		1b	= Force INT# assertion.
		000b		= no pulse stretching.
		001b		= 21 ms to 42 ms.
		010b		= 42 ms to 84 ms.
Pulse stretch duration	14:12	01b1		= 84 ms to 170 ms.	R/W	100b	Retain
		100b		= 170 ms to 340 ms.
		101b		= 340 ms to 670 ms.
		110b = 670 ms to 1.3 s.
		111b = 1.3s to 2.7 s.
Disable LED	15	0b	= Enable.		R/W	0b	Retain
		1b	= Disable.

276 Software Developer’s Manual