Intel PCI-X manual TCP Segmentation Use of Multiple Data Descriptors

Contents
		3.2.5	Receive Descriptor Write-Back	26
		3.2.6	Receive Descriptor Queue Structure	26
		3.2.7	Receive Interrupts	28
		3.2.8	82544GC/EI Receive Interrupts	31
		3.2.9	Receive Packet Checksum Offloading	31
	3.3	Packet Transmission		34
		3.3.1	Transmit Data Storage	35
		3.3.2	Transmit Descriptors	35
		3.3.3	Legacy Transmit Descriptor Format	36
		3.3.4	Transmit Descriptor Special Field Format	40
		3.3.5	TCP/IP Context Transmit Descriptor Format	41
		3.3.6	TCP/IP Context Descriptor Layout	42
		3.3.7	TCP/IP Data Descriptor Format	46
	3.4	Transmit Descriptor Ring Structure		51
		3.4.1	Transmit Descriptor Fetching	53
		3.4.2	Transmit Descriptor Write-back	53
		3.4.3	Transmit Interrupts	54
	3.5	TCP Segmentation		55
		3.5.1	Assumptions	56
		3.5.2	Transmission Process	56
		3.5.3	TCP Segmentation Performance	57
		3.5.4	Packet Format	57
		3.5.5	TCP Segmentation Indication	58
		3.5.6	TCP Segmentation Use of Multiple Data Descriptors	59
		3.5.7	IP and TCP/UDP Headers	60
		3.5.8	Transmit Checksum Offloading with TCP Segmentation	64
		3.5.9	IP/TCP/UDP Header Updating	65
	3.6	IP/TCP/UDP Transmit Checksum Offloading		68
4	PCI Local Bus Interface			71
	4.1	PCI Configuration		71
		4.1.1	PCI-X Configuration Registers	79
		4.1.2	Reserved and Undefined Addresses	82
		4.1.3	Message Signaled Interrupts	83
	4.2	Commands		85
	4.3	PCI/PCI-X Command Usage		87
		4.3.1	Memory Write Operations	87
		4.3.2	Memory Read Operations	89
	4.4	Cache Line Information		90
		4.4.1	Target Transaction Termination	91
	4.5	Interrupt Assignment (82547GI/EI Only)		91
	4.6	LAN Disable		91
	4.7	CardBus Application (82541PI/GI/EI Only)		92
5	EEPROM Interface			93
	5.1	General Overview		93
	5.2	Component Identification Via Programming Interface		94
	5.3	EEPROM Device and Interface		95
		5.3.1	Software Access	96
	5.4	Signature and CRC Fields		96
vi			Software Developer’s Manual