Register Descriptions

Table 13-28. 1000BASE-T Control Register Bit Description

Bit(s)

Field

 

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

 

 

 

000b

= Normal Mode.

 

 

 

 

 

001b

= Test Mode 1 - Transmit

 

 

 

 

 

Waveform Test.

 

 

 

 

 

010b

= Test Mode 2 - Transmit Jitter

 

 

 

15:13

Test mode

Test (MASTER mode).

R/W

000b

000b

011b = Test Mode 3 - Transmit Jitter

 

 

 

 

 

 

 

Test (SLAVE mode).

 

 

 

 

 

100b

= Test Mode 4 - Transmit

 

 

 

 

 

Distortion Test.

 

 

 

101b, 110b, 111b = Reserved.

1.For the 82541xx and 82547GI/EI, only when PHY register 9, bit 12 is set to a logical 0.

2.0b for the 82541xx and 82547GI/EI only

3.For the 82541xx and 82547GI/EI, only when PHY register 9, bit 12 is set to a logical 1.

NOTES:

1.Values programmed in bits 12:8 of the 1000BASE-T Control Register have no effect unless Auto-Negotiation is restarted (PHY Control Register, bit 9) or the link goes down. These bits can also be overridden by the PHY Control Register.

2.The symbol “!” is equivalent to logical “not.”

3.For the 82541xx and 82547GI/EI, the default for bit 9 is affected by configuration bits in the EEPROM. If EEPROM ANI1000DIS is asserted, then the default is set to 0b. If EEPROM ADV10LU is asserted, then the default is set to 0b.

13.4.7.1.111000BASE-T Status Register

GSTATUS (10d; R)

Table 14-29. 1000BASE-T Status Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

Idle Error Count

7:0

Idle Error Counter.

RO,

0000b

0000b

The counter stops at 1111b 1111b and

SC

0000b

0000b

 

 

does not roll over.

 

 

 

 

 

 

 

 

 

 

 

Reserved

9:8

Reserved. Should be set to 00b

RO

00b

00b

 

 

 

 

 

 

 

 

1b = Link Partner is capable of

 

 

 

Link Partner

 

1000BASE-T half duplex.

 

 

 

 

0b = Link Partner is not capable of

 

 

 

1000BASE-T

10

RO

0b

0b

1000BASE-T half duplex.

Half Duplex

 

Values in bits 11:10 are not valid until

 

 

 

Capability

 

 

 

 

 

the ANE Register Page Received bit

 

 

 

 

 

 

 

 

 

 

equals 1b.

 

 

 

 

 

 

 

 

 

 

 

1b = Link Partner is capable of

 

 

 

Link Partner

 

1000BASE-T full duplex.

 

 

 

 

0b = Link Partner is not capable of

 

 

 

1000BASE-T

11

1000BASE-T full duplex.

RO

0b

0b

Full Duplex Capability

 

Values in bits 11:10 are not valid until

 

 

 

 

 

the ANE Register Page Received bit

 

 

 

 

 

equals 1b.

 

 

 

 

 

 

 

 

 

Remote Receiver

12

1b = Remote Receiver OK.

RO

0b

0b

Status

0 b = Remote Receiver Not OK.

 

 

 

 

 

 

 

 

 

 

258

Software Developer’s Manual

Page 272
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Intel Intel Gigabit Ethernet Controllers, PCI-X manual 258