Register Descriptions

13.7.43Total Packets Received

TPR (040D0h; R)

This register counts the total number of all packets received. All packets received are counted in this register, regardless of their length, whether they have errors, or whether they are flow control packets. This register only increments if receives are enabled.

Table 13-132. TPR Register Bit Description

31

 

 

0

 

 

 

TPR

 

 

 

 

 

Field

Bit(s)

Initial

Description

 

Value

 

 

 

 

 

 

 

 

 

 

TPR

31:0

0b

Number of all packets received.

 

 

 

 

 

 

13.7.44Total Packets Transmitted

TPT (040D4h; R)

This register counts the total number of all packets transmitted. All packets transmitted are counted in this register, regardless of their length, or whether they are flow control packets.

Partial packet transmissions (collisions in half-duplex mode) are not included in this register. This register only increments if transmits are enabled. This register counts all packets, including standard packets, secure packets, packets received over the SMBus1, and packets generated by the ASF function.

Table 13-133. TPT Register Bit Description

31

 

 

0

 

 

 

TPT

 

 

 

 

Field

Bit(s)

Initial

Description

Value

 

 

 

 

 

 

 

TPT

31:0

0b

Number of all packets transmitted.

 

 

 

 

1.The 82544GC/EI and the 82541ER do not support SMBus or ASF functionality.

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Software Developer’s Manual

Page 372
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Intel PCI-X manual Total Packets Received, Total Packets Transmitted, TPR 040D0h R, TPT 040D4h R