Register Descriptions

Table 13-20. Auto-Negotiation Advertisement Register Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

 

 

1b = Asymmetric Pause.

 

 

 

 

 

0b = No asymmetric Pause.

 

0b

 

Asymmetric Pause

 

Values programmed in the Auto-

 

 

 

 

 

 

 

Negotiation advertisement register

 

 

 

 

11

have no effect unless Auto-

R/W

1b for the

Retain

 

Negotiation is restarted (PHY Control

ASM_DIR for the

(82541xx

 

Register) or link goes down.

 

 

(82541xx and

 

 

and

 

82547GI/EI)

 

82541xx and 82547GI/EI only:

 

82547GI/

 

 

 

Advertise Asymmetric Pause direction

 

EI)

 

 

 

bit. This bit is used in conjunction with

 

 

 

 

 

PAUSE.

 

 

 

 

 

 

 

 

 

 

 

This bit is reserved and equals 0b.

 

 

 

 

 

Values programmed in the Auto-

 

 

 

 

 

Negotiation advertisement register

 

 

 

 

 

have no effect unless Auto-

 

 

 

Reserved

12

Negotiation is restarted (PHY Control

R/W

0b

Retain

 

 

Register) or link goes down.

 

 

 

 

 

Reserved bit is R/W to allow for

 

 

 

 

 

forward compatibility with future IEEE

 

 

 

 

 

standards.

 

 

 

 

 

 

 

 

 

 

 

1b = Set Remote Fault bit.

 

 

 

 

 

0b = Do not set Remote Fault bit.

 

 

 

Remote Fault

13

Values programmed in the Auto-

R/W

0b

Retain

Negotiation advertisement register

 

 

have no effect unless Auto-

 

 

 

 

 

Negotiation is restarted (PHY Control

 

 

 

 

 

Register) or link goes down.

 

 

 

 

 

 

 

 

 

Reserved

14

Reserved. Should be set to 0b.

RO

Always 0b

 

 

 

 

 

 

 

 

 

1b = Advertise.

 

 

 

 

 

0b = Not advertised.

 

 

 

 

 

Values programmed in the Auto-

 

 

 

 

 

Negotiation advertisement register

 

 

 

 

 

have no effect unless Auto-

 

 

 

 

 

Negotiation is restarted (PHY Control

 

 

 

 

 

Register) or link goes down.

 

 

 

 

 

If 1000BASE-T is advertised then the

 

 

 

Next Page

15

required next pages are automatically

R/W

0b

Retain

 

 

transmitted. The Next Page bit should

 

 

 

 

 

equal 0 if no additional next pages are

 

 

 

 

 

needed.

 

 

 

 

 

82541xx and 82547GI/EI only:

 

 

 

 

 

1b = Manual control of Next Page

 

 

 

 

 

(Software).

 

 

 

 

 

0b = Ethernet controller control of Next

 

 

 

 

 

Page (Auto).

 

 

 

 

 

 

 

 

 

1.For the 82541xx and 82547GI/EI, if EEPROM bit ADV10LU is asserted, then the default is set to 0b. Otherwise, the default is 1b.

Software Developer’s Manual

249

Page 263
Image 263
Intel Intel Gigabit Ethernet Controllers, PCI-X manual 82541xx 82547GI/EI 82541xx and 82547GI/EI only