Fiber Copper 82544GC/EI, Ipgt IPGR1 IPGR2 | Intel PCI-X specs

General Initialization and Reset Operation

•Configure the Collision Threshold (TCTL.CT) to the desired value. Ethernet standard is 10h. This setting only has meaning in half duplex mode.

•Configure the Collision Distance (TCTL.COLD) to its expected value. For full duplex operation, this value should be set to 40h. For gigabit half duplex, this value should be set to 200h. For 10/100 half duplex, this value should be set to 40h.

Program the Transmit IPG (TIPG) register with the following decimal values to get the minimum legal Inter Packet Gap:

	Fiber	Copper	Fiber	Copper
	Fiber	Copper	(82544GC/EI	(82544GC/EI
			(82544GC/EI	(82544GC/EI

IPGT	10	10	6	8

IPGR1	10	10	8a	8a
IPGR2	10	10	6a	6a

a.Applicable to the 82541xx and 82547GI/EI.

374	Software Developer’s Manual

Image 388

Intel PCI-X, Intel Gigabit Ethernet Controllers manual Fiber Copper 82544GC/EI, Ipgt IPGR1 IPGR2

Contents

82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, Software Developer’s Manual Date Version Comments Initial Public Release Software Developer’s Manual Contents TCP Segmentation Use of Multiple Data Descriptors Software Developer’s Manual Vii Power Management 129 Introduction to Power Management 10.1.3 203 13.4.25 13.7.10 Appendix 82540EP/EM and 82545GM/EM Differences Xiv Scope Overview Ethernet Controller Features PCI FeaturesCSA Features 82547GI/EI Only Network Side Features Host Offloading Features Additional Performance Features Additional Ethernet Controller Features Technology Features Conventions Related DocumentsMemory Alignment Terminology Register and Bit References Architectural Overview Introduction PHY External ArchitectureLAN a LAN B ECHO, Next Fext Eeprom FlashAGC, A/D Microarchitecture 1 PCI/PCI-X Core Interface 2 82547GI/EI CSA Interface DMA Engine and Data Fifo 4 10/100/1000 Mb/s Receive and Transmit MAC Blocks 5 MII/GMII/TBI/Internal SerDes Interface Block 6 10/100/1000 Ethernet Transceiver PHY Eeprom Interface DMA Addressing Flash Memory InterfaceExample 2-1. Byte Ordering Little Endian Data Ordering Intel Architecture Byte Ordering Ethernet AddressingIA Byte # LSB MSB Interrupts Hardware Acceleration Capability Buffer and Descriptor StructureChecksum Offloading TCP Segmentation Architectural Overview Packet Reception IntroductionPacket Address Filtering Receive Descriptor Format Receive Data StorageReceive Descriptor Rdesc Layout Receive Descriptor Status Field Receive Status RDESC.STATUS LayoutPIF Ipcs Tcpcs RSV Ixsm EOP Receive Receive Descriptor Errors Field Receive Errors RDESC.ERRORS Layout RXE IPE Tcpe RSVRSV SEQ CXE Receive Descriptor Special Field Special Descriptor Field LayoutPRI CFI Vlan PRI Receive Descriptor Fetching Receive Descriptor Fetching Algorithm Receive Descriptor Write-Back Receive Descriptor Queue StructureReceive Descriptor Packing Null Descriptor Padding Receive Descriptor Ring Structure Receive Interrupt Delay Timer / Packet Timer Rdtr Receive Timer InterruptReceive Interrupts Receive Interrupt Absolute Delay Timer Radv Packet Delay Timer Operation State Diagram Small Receive Packet Detect 8 82544GC/EI Receive Interrupts Receive Packet Checksum OffloadingReceive Descriptor Minimum Threshold ICR.RXDMT Receiver Fifo Overrun Supported Receive Checksum Capabilities Packet Type HW IP Checksum HW TCP/UDP Checksum Calculation MAC Address Filter GC/EI Supported Receive Checksum CapabilitiesPacket Type HW IP Checksum HW TCP/UDP Checksum Packet Type HW IP Checksum Packet Transmission SNAP/VLAN Filter9.3 IPv4 Filter 9.4 IPv6 Filter Transmit Data Storage Transmit Descriptors Transmit Descriptor Tdesc Layout Legacy Mode Legacy Transmit Descriptor FormatTransmit Descriptor Tdesc Layout Transmit Descriptor Legacy Descriptions Transmit Descriptor Description Legacy CMDSTA CSS Transmit Descriptor Command Field Format 10. Transmit Command TDESC.CMD LayoutIDE VLE Dext RSV Ifcs EOP Transmit Descriptor Status Field Format 11. Transmit Status Layout Transmit Descriptor Special Field Format 12. Special Field TDESC.SPECIAL Layout 5 TCP/IP Context Transmit Descriptor Format 6 TCP/IP Context Descriptor Layout 13. Transmit Descriptor Tdesc Layout Type = 0000b 14. Transmit Descriptor Tdesc Layout Transmit Description Descriptor Offload 6.1 TCP/UDP Offload Transmit Descriptor Command Field Transmit DescriptionTucmd Dtyp IDE RSV Dext TSE TCP 15. Command Field TDESC.TUCMD Layout82544GC/EI only 6.2 TCP/UDP Offload Transmit Descriptor Status Field 7 TCP/IP Data Descriptor Format16. Transmit Status Layout Popts RSV STA Dcmd Dtyp Dtalen 17. Transmit Descriptor Tdesc Layout Type = 0001bPopts 7.1 TCP/IP Data Descriptor Command Field 18. Command Field TDESC.DCMD LayoutIDE VLE Dext TSE Ifcs EOP 19. Transmit Status Layout 7.2 TCP/IP Data Descriptor Status FieldReserved 7.3 TCP/IP Data Descriptor Option Field 7.4 TCP/IP Data Descriptor Special Field20. Packet Options Field TDESC.POPTS Layout RSV Txsm Ixsm Transmit Descriptor Ring Structure 21. Special Field TDESC.SPECIAL Layout Transmit Descriptor Ring Structure Transmit Descriptor Fetching Transmit Descriptor Write-back Transmit Interrupts Delayed Transmit Interrupts Assumptions Transmission Process TCP Segmentation Performance Packet FormatTCP Segmentation Data Fetch Control TCP/UDP Data FCS TCP Segmentation Indication 3936 TCP Segmentation Use of Multiple Data Descriptors TCP Partial Pseudo-Header Checksum Version IP Hdr IP and TCP/UDP HeadersOptions Fragment Offset Low Type of service Version IP Hdr Length FragmentOffset High Header Checksum Destination Port Sequence Number TCP HeaderLength Checksum Urgent Pointer Options Byte1 Byte0 Destination Port Source Port Destination Port Length Checksum Byte3 Byte2 Byte1 Byte0 17. UDP Pseudo Header Diagram for IPv4 Transmit Checksum Offloading with TCP Segmentation 9 IP/TCP/UDP Header Updating 19. Overall Data Flow 9.1 TCP/IP/UDP Header for the First Frame 9.2 TCP/IP/UDP Header for the Subsequent Frames IP/TCP/UDP Transmit Checksum Offloading 9.3 TCP/IP/UDP Header for the Last Frame Ipcss Receive and Transmit Description PCI Configuration Mandatory PCI RegistersAddress Description PCI Specification Update for the latest stepping information Base Address Registers Addr All base address registers have the following fields Field Bits Read Initial Description Write Value Expansion ROM Base Address Offset Space Capabilities Linked List Address Next Pointer PCI definition for more details Bits Initial Value Description Status Register Layout 82547GI/EI PCI-X Configuration Registers PCI-X Capability IDNext Capability Byte Offset PCI-X Command Bits Read InitialWrite Value Maximum Memory Read Byte Count. This register sets USC SCD PCI-X StatusBits Read Intial Description Write Value Command Register as follows Reserved and Undefined Addresses Message Signaled Interrupts1 Message Signaled Interrupt Configuration RegistersMSI Capability ID Bits Read Initial Description Write Value 05h Message Control Commands 3.1.4 Message Address3.1.5 Message Upper Address 3.1.6 Accepted PCI/PCI-X Command as a Target PCI Commands Abr PCI-X CommandsTransaction Target PCI Commands PCI-X Commands Transaction Cause PCI Commands PCI-X Commands PCI/PCI-X Command Usage Memory Write Operations Master Write Command Usage Algorithm MWI Bursts PCI-X Command Usage Memory Read OperationsMW Bursts Rules for Memory Read Operations Cache Line Information1 Outstanding Memory Read Interrupt Assignment 82547GI/EI Only LAN DisableTarget Transaction Termination CardBus Application 82541PI/GI/EI Only Eeprom Interface General Overview Component Identification Component Identification Via Programming InterfaceStepping Vendor ID Device ID Description Eeprom Device and Interface Software Access Signature and CRC Fields Eeupdate Utility Command Line Parameters Eeprom Address Map1 Ethernet Controller Address MapWord Used Bit Image For the 82541xx and 82547GI LAN a 82545GM 82540EP82541xx and 82547GI/EI only 82546GB/EB only 82541xx 82545GM 82540EP/EM ASF GC/EI and 82541ER Eeprom Address Map Word Description Default HW AccessAddress Hi Byte Low Byte Ethernet Address Words 00h-02h Software Compatibility Word Word 03hSoftware Compatibility Word Word 03h Bit Name Description SerDes Configuration Word 04h Eeprom Image Version Word 05hCompatibility Fields Word 05h 07h PBA Number Word 08h, 09h Initialization Control Word 1 Word 0Ah Initialization Control Word 1 Word 0Ah Subsystem ID Word 0Bh Subsystem Vendor ID Word 0Ch Device ID Word 0Dh, 11h1 Vendor ID Word 0EhInitialization Control Word 2 Word 0Fh Initialization Control Word 2 Word 0Fh 82541PI/GI Only Common Power Word 12h Software Defined Pins Control Word 10h1, 20hPHY Register Address Data Words 10h, 11h, and 13h 1Eh OEM Reserved Words Words 10h, 11h, 13h 1Fh Software Defined Pins Control Word 10h, 20h CSA Port Configuration 2 Word 21h CSA Port Configuration 2 Word 21hBit Description Default 20 D0 Power Word 22h high byte 21 D3 Power Word 22h low byteCircuit Control Word 21h Reserved Words 23h 2Eh Management Control Word 13h1, 23h2 10. Initial Management Control Register Settings82541PI/GI/EI and 82547GI/EI Only SMBus Slave Address Word 14h1 low byte, 24h low byte 11. SMBus Slave Address Initialization Control 3 Word 14h1 high byte, 24h high byte 12. Initialization Control82546GB/EB uses INTB# For Address 24h High Byte / LAN a LED Configuration Defaults Word 2Fh2 Boot Agent Main Setup Options Word 30h27 IPv4 Address Words 15h 16h1 and 25h 26h 28 IPv6 Address words 17h 1Eh1 and 27h 2Eh 15. Boot Agent Main Setup Options DBS Boot Agent Configuration Customization Options Word 31hBBS 16. Boot Agent Configuration Customization Options Word 31h SIGMode DFU Boot Agent Configuration Customization Options Word 32h 17. Boot Agent Configuration Customization Options Word 32h IBA Capabilities Word 33h IBA Secondary Port Configuration Words 34h-35h18. IBA Capabilities 19. WOL Mode and Functionality Word 0Ah 20. WOL Mode and Functionality Word 20hChecksum Word Calculation Word 3Fh Eeprom Images Parallel Flash Memory 21. Flash Memory ManufacturersManufacturer Number 124 Flash Control and Accesses Flash Interface Operation Read Accesses Write Accesses Flash Buffer Write Cycle 128 Introduction to Power Management Assumptions Power States D3cold support Dr State 1.2 D0u State 1.3 D0a D0 active Timing1.4 D3 Power Up Off to Dr to D0u to D0a Diagram # Transition From D0a to D3 and Back Without PCI Reset Transition from D0a to D3 and Back Without PCI Reset Transition From D0a to D3 and Back with PCI Reset RST# PCI Reset Without Transition to D3 PCI Reset Sequence PCI Power Management Registers Bits Default DescriptionCapability ID Byte Offset = 0 RO Next Item Pointer Byte Offset = 1 RO Reserved Power Management Capabilities PMC 2 Bytes Offset = 2 ROEeprom Software Developer’s Manual 139 Pmcsrbse Bridge Support Extensions 3.6 Data RegisterByte Offset = 6 RO Byte Offset = 7 RO Advanced Power Management Wakeup Wakeup Acpi Power Management Wakeup Pre-Defined Filters Wakeup PacketsDirected Exact Packet 3.1.3 Broadcast Directed Multicast Packet3.1.4 Magic Packet*1 Offset Field Value Action Comment Offset Field Value Action Comment Bytes 3.1.5 ARP/IPv4 Request Packet1 + S a+ D + S a ARP Directed IPv4 Packet1 Offset # of bytes Field Value Action Comment Directed IPv6 Packet1 IPX Diagnostic Responder Request Packet Example1 Flexible Filter+ S + D + S Directed IPX Packet Example 3.4 IPv6 Neighbor Discovery Filter1 Wakeup Packet Storage CRC 152 Ethernet Interface Link Interfaces Overview Internal SerDes Interface/TBI Mode- 1Gb/s1 1.2 8B10B Encoding/Decoding Gmii 1 Gb/s Code Groups and Ordered SetsCode Group and Ordered Set Usage Code OrderedSet Duplex Operation Internal Interface1MII 10/100 Mb/s Full Duplex Half Duplex Carrier Extension 1000 Mb/s Only Packet Bursting Auto-Negotiation and Link Setup1 Auto-Negotiation and Link Setup2 Link Speed Link Configuration in Internal Serdes/TBI Mode1Auto-Negotiation TXCW.txConfigWord Hardware Auto-Negotiation Software Auto-Negotiation Bit Description Internal GMII/MII Mode Forcing Link Using Auto-Speed Detection ASD Forcing Speed Automatic Detection of Link Speed using SPD-IND DuplexMII Management Registers Comments Regarding Forcing Link Internal SerDes Mode1 Control Bit Resolution Internal Serdes Mode1 Hardware EnabledInternal Serdes1 Mode Software Enabled Control Bit Effect on Control Bits GMII/MII Mode PHY Speed Indication Internal PHY Mode Control Bit ResolutionInternal Serdes Mode1 Auto-Negotiation Skipped GMII/MII Mode Auto-Speed Detection GMII/MII Mode Force Speed Loss of Signal/Link Status Indication Internal Serdes ModeInternal PHY Mode GMII/MII Mode Force Link 10/100 Mb/s Specific Performance Enhancements Adaptive IFS1 Flow Control MAC Control Frames & Reception of Flow Control Packets10. Flow Control Registers Register Name Description 3x MAC Control Frame Format Discard Pause Frames and Pass MAC Control Frames Transmission of Pause Frames Software Initiated Pause Frame Transmission External Control of Flow Control Operation1 802.1q Vlan Packet Format 1 802.1q Tagged FramesVlan Packet Format Comparison Packet #Octets Transmitting and Receiving 802.1q Packets 802.1q Vlan Packet FilteringAdding 802.1q Tags on Transmits Stripping 802.1q Tags on Receives Packet Reception Decision Table VFE 178 Configurable LED Outputs1 Selecting an LED Output Source Polarity Inversion Blink Control Blink Control 182 PHY Functionality and Features Auto-Negotiation Register Update Next Page Exchanges 11.2 MDI/MDI-X Crossover copper only StatusPin 1000BASE-T Polarity Correction copper only 11.2.2 10/100 Downshift 82540EP/EM Only Cable Length Detection copper only PHY Power Management copper onlyLink Down Energy Detect copper only 11.4.4 D3 Link-Up, Speed-Management Disabled copper only 11.4.3 D3 Link-Up, Speed-Management Enabled copper only11.4.2 D3 State, No Link Required copper only Mdio Control Mode Initialization Determining Link State Overview of Link Establishment Configuration Result False LinkForced Operation Determining Duplex State Via Parallel Detection Link Criteria Auto NegotiationParallel Detection 11.7.1 1000BASE-T Using SmartSpeed Link Enhancements11.7.3 10BASE-T SmartSpeed Low Power Operation Pause And Asymmetric Pause SettingsAsmdir Settings Pause Setting Management Data Interface Smart Power-Down Powerdown via the PHY Register11.11 1000 Mbps Operation DSP ECHO, Next 4DPAM5 Transmit Functions Transmit Fifo Spectral Shaper Low-Pass FilterLine Driver Transmit/Receive Flow Receive Functions 11.12 100 Mbps Operation 11.13 10 Mbps OperationDescrambler Viterbi Decoder/Decision Feedback Equalizer DFE PHY Line Length Indication 202 Introduction1 Features of Each MAC12.2.1 PCI/PCI-X interface 204 12.2.3 SDP, LED, INT# output MAC Configuration Register SpaceIO BAR Eeprom Map Shared EepromEeprom Arbitration Flash Access Contention Shared Flash Values Sampled on Reset Pin sampled LAN device controlled Enable/Disable Multi-Function Advertisement Power ReportingInterrupt Use Enabled SummaryInterrupt Line Used INTA# Register Descriptions Register Conventions Memory-Mapped Access to Internal Registers and Memories Memory-Mapped Access to FlashMemory-Mapped Access to Expansion ROM Memory and I/O Address Decoding Ioaddr IodataOffset Abbreviation Name Size Ioaddr Iodata Register Configurations AD C/BE#30 Bits Ethernet Controller Register Summary Category Offset Abbreviation Name82544GC/EI 82547GI/EI only Ipat 82544GC Xofftxc FcrucPRC64 Gprc Category Abbreviation Name Register82544GC/EI , 82541xx , or 82547GI/EI To the 82544GC/EI , 82541xx , or 82547GI PCI-X Register Access Split1 Device Control Register Main Register DescriptionsCtrl 00000h R/W Ctrl Register Bit Description Field Bits Initial Description Value Ilos SLUSpeed Frcdplx SDP0DATASDP1DATA ADVD3WUC Field Bits Initial Description BEM = 0 64-bit mode Little-Endian Device Status RegisterStatus 00008h R Little-Endian Data Ordering Txoff Status Register Bit DescriptionTbimode Asdv PCI66Pcixmode Pcixspd EEPROM/Flash Control & Data Register Eecd 00010h R/WEecd Register Bit Description 82544GC/EI Only Eereq EegntEepres Eesize Eerd 00014h RW Eeprom Read Register1Eeprom Read Register Bit Description Eeprom Read Register Bit Description 82541xx and 82547GI/EI Done Start Flash Access FLA Flash Access1FLA 0001Ch R/W Extended Device Control Register Ctrlext 00018h, R/W10. Ctrlext Register Bit Description 23 16 SDP6IODIR SDP2IODIRSDP7IODIR Asdchk Vreg Power 11. GPI to SDP Bit MappingsDown Linkmode Swdpinshi 12 GC/EI Ctrlext Register Bit DescriptionSwdpiohi CTRL.RST 13 GC/EI GPI to SDP Bit Mapping MDI Control Register Mdic 00020h R/W 14. MDI Control Register Bit Description RSV PHY REG DataRegadd Phyadd Register Mode Description 15. PHY Register Bit Mode DefinitionsPHY Registers Field Bits Description Mode HW Rst SW Rst MSB 242 Enaxc LSB RO,L Software Developer’s Manual 245 246 For the 82541xx and 82547GI/EI 82544GC/EI only 82541xx Pause 82541xx 82547GI/EI 82541xx and 82547GI/EI only 82544GC/EI Only ANEG3ANEG2 RF1 Software Developer’s Manual 251 23. Link Partner Ability Register Base Page Bit Description1 82541xx and 82547GI/EI Only 24. PHY Link Page Ability Bit Description110BASE-T 100BASE-TX 1b 82541xx Software Developer’s Manual 255 Bits Field Description Mode HW Rst SW Rst Master ANEG0MASTER/SLAVE ANEG1 258 Software Developer’s Manual 259 DIS NLP Preen SFD Software Developer’s Manual 263 264 Software Developer’s Manual 265 266 82541EI/82547GI B0 stepping 82541/GI/ER and 82547GI B1 268 HCD NOK Software Developer’s Manual 271 272 Field Bits Description Mode HW Rst Ledactled SPEED100LED SPEED1000LED 276 Software Developer’s Manual 277 51. MDI Register 30 Operations Documented MDI Register 30 Operations1To Perform Operation MDI Read/Write Sequence Flow Control Address Low Flow Control Address HighFcal 00028h R/W Fcah 0002Ch R/W Flow Control Type Vlan Ether TypeFCT 00030h R/W VET 00038h R/W Flow Control Transmit Timer Value Fcttv 00170h R/W56. VET Register Bit Description 57. Fcttv Register Bit Description Txcw 00178h R/W Transmit Configuration Word Register158. Txcw Register Bit Description Receive Configuration Word Register1 Rxcw 00180h R 59. Rxcw Register Bit Description LED Control1 Ledctl 00E00h RWANC LED1 ACTIVITY# LED0 LINKUP# Mode Encodings for LED Outputs1 60. LED Control Bit Description1 61. Mode Encodings for LED Outputs Mode Pneumonic State / Event Indicated Packet Buffer Allocation PBA 01000H R/W62. PBA Register Bit Description Field Bits Initial Value Description ICR 000C0H R Interrupt Cause Read Register63. ICR Register Bit Description RXT0 MdacRxcfg GPISDP6 ITR 000C4h R/W Interrupt Throttling Register1Interval ICS 000C8h W Interrupt Cause Set Register64. ICS Register Bit Description Interrupt Mask Set/Read Register IMS 000D0h R/W65. IMS Register Bit Description To the 82544GC/EI Interrupt Mask Clear Register IMC 000D8h W 66. IMC Register Bit Description Receive Control Register Rctl 00100h R/W67. Rctl Register Bit Description SBP MPE LPELBM Rdmts BAM BsizeVFE Cfien Bsex PmcfSecrc XON Enable 82544GC/EI , 82541xx , and 82547GI/EI only Flow Control Receive Threshold LowFcrtl 02160h R/W 68. Fcrtl Register Bit Description Fcrth 02168h R/W Flow Control Receive Threshold High69. Fcrth Register Bit Description Receive Descriptor Base Address Low Receive Descriptor Base Address HighRdbal 02800hR/W Rdbah 02804h R/W Receive Descriptor Length Receive Descriptor HeadRdlen 02808h R/W RDH 02810h R/W Receive Delay Timer Register Receive Descriptor TailRDT 02818hR/W Rdtr 02820h R/W Receive Interrupt Absolute Delay Timer1 Radv 0282Ch RW Receive Small Packet Detect Interrupt1 Transmit Control RegisterRsrpd 02C00h R/W Tctl 00400hR/W 76. Tctl Register Bit Description ColdPSP TCTL.COLD Transmit IPG Register Tipg 00410R/WRtlc Nrtu 77. Tipg Register Bit Description IPGR2 IPGR1 Ipgt Aifs 00458R/W Adaptive IFS Throttle AITIPGR2 Transmit Descriptor Base Address Low Tdbal 03800h R/W78. Aifs Register Bit Description 79. Tdbal Register Bit Description Transmit Descriptor Base Address High Transmit Descriptor LengthTdbah 03804h R/W Tdlen 03808h R/W TDH 03810h R/W Transmit Descriptor Head82. TDH Register Bit Description Transmit Interrupt Delay Value Transmit Descriptor TailTDT 03818h R/W Tidv 03820h R/W TX DMA Control 82544GC/EI only Transmit Descriptor ControlTxdmac 03000h R/W Txdctl 03828h R/W 86. Txdctl Register Bit Description Lwthresh RSV1 Gran RSV Wthresh Hthresh Pthresh Transmit Absolute Interrupt Delay Value1 Tadv 0382Ch RWGran Lwthresh Tspbp Tsmt TCP Segmentation Pad And Minimum Threshold Tspmt 03830h RWTspbp Software Developer’s Manual 319 Receive Descriptor Control Rxdctl 02828h R/W87. Rxdctl Register Bit Description Wthresh RSV Hthresh Pthresh Receive Checksum Control Rxcsum 05000h R/W88. Rxcsum Register Bit Description 3111 Tuofld IpofldIPV6OFL Filter Registers Multicast Table ArrayMTA1270 05200h-053FCh R/W 89. MTA Register Bit Description Destination Address Receive Address Low Receive Address HighRAL 05400h + 8*n R/W RAH 05404h + 8∗n R/W Vlan Filter Table Array1 VFTA1270 05600h 057FCh R/W91. RAH Register Bit Description RAH Wakeup Registers Wakeup Control RegisterWUC 05800h R/W 92. VFTA1270 Bit Description Wakeup Filter Control Register Wufc 05808h R/WApmpme SPM Wakeup Status Register WUS 05810h R 330 IP Address Valid Ipav 5838h R/W 13.6.5 IPv4 Address IP4AT 05840h 05858h R/W2Address Field Dword # Address Bits Initial Value Description 13.6.6 IPv6 Address IP6AT 05880h 0588Ch R/WIPV6ADDR0 Dword # Address Bits Initial Value Description Wakeup Packet Memory 128 Bytes Wakeup Packet LengthFlexible Filter Length Table Flexible Filter Mask Table Ffmt 09000h 093F8h R/W LEN0LEN1 LEN2 Flexible Filter Value Table Statistics RegistersFfvt 09800h 09BF8h R/W CRC Error Count Alignment Error CountCrcerrs 04000h R Algnerrc 04004h R Symbol Error Count RX Error CountSymerrs 04008h R Rxerrc 0400Ch R Missed Packets Count Single Collision CountMPC 04010h R SCC 04014h R Excessive Collisions Count Multiple Collision CountEcol 04018h R MCC 0401Ch R Late Collisions Count Collision CountLatecol 04020h R Colc 04028h R Defer Count Transmit with No CRSDC 04030h R Tncrs 04034h R Sequence Error Count Carrier Extension Error CountSEC 04038h R Cexterr 0403Ch R Receive Length Error Count XON Received CountRlec 04040h R Xonrxc 04048h R Xoff Received Count XON Transmitted CountXoff Transmitted Count FC Received Unsupported Count Packets Received 64 Bytes CountFcruc 04058h R PRC64 0405Ch R Packets Received 65-127 Bytes Count Packets Received 128-255 Bytes CountPRC127 04060h R PRC255 04064h R Packets Received 256-511 Bytes Count Packets Received 512-1023 Bytes CountPRC511 04068h R PRC1023 0406Ch R Packets Received 1024 to Max Bytes Count Good Packets Received CountPRC1522 04070h R Gprc 04074h R Broadcast Packets Received Count Multicast Packets Received CountBprc 04078h R Mprc 0407Ch R Good Packets Transmitted Count Good Octets Received CountGptc 04080h R Gorcl 04088h R/GORCH 0408Ch R Good Octets Transmitted Count Receive No Buffers CountGotcl 04090h R/ Gotch 04094 R Rnbc 040A0h R Receive Undersize Count Receive Fragment CountRUC 040A4h R RFC 040A8h R Receive Oversize Count Receive Jabber CountROC 040ACh R RJC 040B0h R Mgtprc 040B4h R Management Packets Received Count1129. RJC Register Bit Description Management Pkts Transmitted Count1 Management Packets Dropped Count1Total Octets Received Total Octets Transmitted Totl 040C8h R/W / Toth 040CCh R130. Torl and Torh Register Bit Descriptions 131. Totl and Toth Register Bit Descriptions Total Packets Received Total Packets TransmittedTPR 040D0h R TPT 040D4h R Packets Transmitted 64 Bytes Count Packets Transmitted 65-127 Bytes CountPTC64 040D8h R PTC127 040DCh R Packets Transmitted 128-255 Bytes Count Packets Transmitted 256-511 Bytes CountPTC255 040E0h R PTC511 040E4h R Packets Transmitted 512-1023 Bytes Count Packets Transmitted 1024 Bytes or Greater CountPTC1023 040E8h R PTC1522 040ECh R Multicast Packets Transmitted Count Broadcast Packets Transmitted CountMptc 040F0h R Bptc 040F4h R TCP Segmentation Context Transmitted Count TCP Segmentation Context Transmit Fail CountTsctc 040F8h R Tsctfc 040FCh R Diagnostics Registers Receive Data Fifo Head RegisterReceive Data Fifo Tail Register Rdfh 02410h R/W Receive Data Fifo Head Saved Register Receive Data Fifo Tail Saved RegisterRdfhs 02420h R/W Rdfts 02428h R/W Receive Data Fifo Packet Count Transmit Data Fifo Head RegisterRdfpc 02430h R/W Tdfh 03410h R/W Transmit Data Fifo Tail Register Transmit Data Fifo Head Saved RegisterTdft 03418h R/W Tdfhs 03420h R/W Transmit Data Fifo Tail Saved Register Transmit Data Fifo Packet CountTdfts 03428h R/W Tdfpc 03430h R/W Packet Buffer Memory PBM 10000h 1FFFCh R/W151. Tdfpc Register Bit Description 152. PBM Bit Description 370 Power Up State General Configuration General Initialization and Reset Operation Receive Initialization Transmit Initialization Fiber Copper 82544GC/EI Ipgt IPGR1 IPGR2 Signal Descriptions Signal Ball Name and Function Signal Interface Carrier SenseReceive Data Receive Clock GMII/MII Features not Supported Signal FunctionsSignal Function Pin Gmii 1000 Mbps Operations MII 10/100 Mbps Differences Signal Functions Not Supported Avoiding Gmii Test Modes MAC ConfigurationDirect PHY Indications to MAC Link Setup CTRL.FD PHY Initialization 10/100/1000 Mb/s Copper Media CTRL.RFCE Reset Operation Lanpwrgood 382 Software Developer’s Manual 383 Initialization of Statistics Diagnostics Fifo StateFifo Data Loopback Testability Internal Loopback Extest Instruction SAMPLE/PRELOAD InstructionIdcode Instruction Bypass Instruction 388 New Features Appendix Changes From 82544EI/82544GC Register Changes Table A-1. Register ChangesRegister Offset EEC 82540EP/EM Differences Serial Flash Interface Single-Port Functionality No TBI/Internal SerDes Interface4 32-Bit PCI Support