Intel PCI-X manual MWI Bursts, Master Write Command Usage Algorithm

PCI Local Bus Interface

	IDLE
	Wr_Req (Cnt_Rmn != 0)
	Write Command
Aligned && (Count >= CLS)	Determination	!Aligned (Aligned && (Count < CLS)) !MWI_Enable
MWI	Cnt_Rmn = 0	MW
Burst*		Burst

	Cnt_Rmn = 0
	Terminate
Boundary Terminate	Transaction
MWI_Enable &&	Terminate
d && Cnt_Rmn >= CLS)
	!MWI_Enable

MWI

Boundary

Evaluation

* Either the initiation or continuation of the MWI Burst

(!Aligned Cnt_Rmn < CLS)

Count = Amount of data for XFR Cnt_Rmn = Remaining data for XFR Wr_Req = Initial request for master write CLS = Cache line size

Boundary = At cache line boundary?

Aligned = Address aligned to cache line boundary Terminate = Target disconnect or latency timer e

Figure 4-4. Master Write Command Usage Algorithm

4.3.1.1MWI Bursts

•If there is at least one cache line of data remaining, then the Ethernet controller continues the MWI burst.

•If there is not at least one cache line of data remaining, then the Ethernet controller terminates the transaction on the boundary, re-acquires the bus, and issues a MW command for the remainder of data.

•If the transaction is terminated prematurely due to a target disconnect or latency time-out, the Ethernet controller re-evaluates command usage based on the new start address and the amount of remaining data.

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