Intel Intel Gigabit Ethernet Controllers, PCI-X manual Destination Address

Register Descriptions

Of the 16 bits, look at bits 11:5, starting from zero. These seven bits corresponds to the row within the MTA table (the MTA has 128 rows which require seven bits to define). In the example, bits 11:5 are 1011110b. This corresponds to row 94.

Of these 16 bits, count out the first five bits, again starting from bit zero. These first five bits correspond to the bit within the row (the MTA is 32 bits wide which require five bits to define). In the example this is 01001b. This corresponds to bit nine. This is the offset within the row.

Therefore, software needs to set bit nine of row 94 in the MTA. If the OS removes this address from the filter list, software would need to clear this bit. This is the same bit that the hardware would check if it received a packet with an address of xx:xx:xx:xx:9x:BCh.

Destination Address

47:40 39:32 31:24

23:16

15:8

7:0

bank[1:0]

	Multicast Table
word	Array 32 x 128
	(4096-bit vector)
pointer[11:5]		?
	...
	...
bit
pointer[4:0]

Figure 13-2. Multicast Table Array

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