Intel Intel Gigabit Ethernet Controllers manual PCI-X Command, Bits Read Initial, Write Value

PCI Local Bus Interface

4.1.1.3PCI-X Command

	15		7	6	4	3	2	1	0
		Reserved		Max. Split Trans-		Read		RO	DP
					actions	Count
Bits	Read	Initial			Description
	Write	Value
			Data Parity Error Recovery Enable. If this bit is 1b, the Ethernet
0	RW	0b	controller attempts to recover from Parity errors. If this bit is 0b, the
			Ethernet controller asserts SERR# (if enabled) whenever the Master
			Data Parity Error bit (Status Register, bit 8) is set.
1	RW	1b	Enable Relaxed Ordering. If this bit is set, the Ethernet controller sets
			the Relaxed Ordering attribute bit in some transactions.
			Maximum Memory Read Byte Count. This register sets the
			maximum byte count the Ethernet controller uses for a Memory Read
			Sequence. The allowable values are:
3:2	RW	0b	Register	Maximum Byte Count
			0		512
			1		1024
			2		2048
			3		4096
			Maximum Outstanding Split Transactions. This register sets the
			maximum number of outstanding split transactions that the Ethernet
			controller uses. The Ethernet controller is only allowed to have one
			outstanding split transaction at any time.
			Register	Maximum Outstanding Transactions
			0		1
6:4	RW	0b	1		2
			2		3
			3		4
			4		8
			5		12
			6		16
			7		32
15:7	R	0b	Reserved. Reads as 0b

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