Register Descriptions

Field

Bit(s)

Initial

Description

Value

 

 

 

 

 

 

 

SDP6_IODIR

 

 

SDP6[2] Pin Directionality. Controls whether software-controllable

 

 

0b1

pin SDP6[2] is configured as an input or output (0b = input, 1b =

SDP2_IODIR

10

output). Initial value is EEPROM-configurable. This bit is not

(82541xx and

 

 

affected by software or system reset, only by initial power-on or

82547GI/EI)

 

 

direct software writes.

 

 

 

 

SDP7_IODIR

 

 

SDP7[2] Pin Directionality. Controls whether software-controllable

 

11

0b1

pin SDP7[2] is configured as an input or output (0b = input, 1b =

SDP2_IODIR

output). Initial value is EEPROM-configurable. This bit is not

(82541xx and

 

 

affected by software or system reset, only by initial power-on or

82547GI/EI)

 

 

direct software writes.

 

 

 

 

 

 

 

ASD Check

 

 

 

Initiate an Auto-Speed-Detection (ASD) sequence to sense the

 

 

 

frequency of the PHY receive clock. The results are reflected in

ASDCHK

12

0b

STATUS.ASDV. This bit is self-clearing.

 

 

 

This functionality is provided for diagnostic purposes, regardless of

 

 

 

whether the Auto Speed Detection feature is enabled. This bit is

 

 

 

applicable only for internal PHY mode of operation.

 

 

 

 

 

 

 

EEPROM Reset

EE_RST

13

0b

When set, initiates a reset-like event to the EEPROM function. This

causes the EEPROM to be read as if a RST# assertion had

 

 

 

occurred. All device functions should be disabled prior to setting

 

 

 

this bit. This bit is self-clearing.

 

 

 

 

Reserved

14

0b1

Reserved. Should be set to 0b.

 

 

 

Speed Select Bypass

 

 

 

When set to 1b, all speed detection mechanisms are bypassed,

 

 

 

and the Ethernet controller is immediately set to the speed

SPD_BYPS

15

0b

indicated by CTRL.SPEED. This can be used to override the

hardware clock switching circuitry and give full control to software.

 

 

 

SPD_BYPS differs from the CTRL.FRCSPD function in that

 

 

 

FRCSPD uses the internal clock switching circuitry rather than an

 

 

 

immediate forcing function of the speed settings, as does

 

 

 

SPD_BYPS.

 

 

 

 

Reserved

16

0b1

Reserved. Should be set to 0b.

 

 

 

Relaxed Ordering Disabled

 

 

 

When set to 1b, the Ethernet controller does not request any

 

 

 

relaxed ordering transactions in PCI-X mode regardless of the

RO-DIS

17

0b

state of bit 1 in the PCI-X command register. When this bit is clear

and bit 1 of the PCI-X command register is set, the Ethernet

 

 

 

 

 

 

controller requests relaxed ordering transactions.

 

 

 

Note: This is a reserved bit for the 82540EP/EM, 82541xx, and

 

 

 

82547GI/EI. Set to 0b.

 

 

 

 

 

 

 

Reserved

Reserved

20:18

0b

Should be written with 0b to ensure future compatibility.

 

 

 

Reads as 0b.

 

 

 

 

234

Software Developer’s Manual

Page 248
Image 248
Intel Intel Gigabit Ethernet Controllers, PCI-X manual SDP6IODIR, SDP2IODIR, SDP7IODIR, Asdchk, Eerst, Spdbyps, Ro-Dis