Intel Intel Gigabit Ethernet Controllers, PCI-X Software Auto-Negotiation, Bit Description

Ethernet Interface

Figure 8-3. 802.3z Advertised Base Page Mapping

Table 8-2. Bits Content in TXCW.txConfigWord

Bit	Description
Np	Next Page Indication
	When set indicates a request for next page exchange
	Asymmetric Pause Connection is Desired
AS	When set, results in independent enabling/disabling of the flow control
	receive and transmit. When cleared, results in symmetric enabling/disabling
	of the flow control receive and transmit
	Pause Function
	When set, indicates that the Ethernet controller is capable and intends to
PS	stop upon reception of 802.3x flow control Pause packets.
	When cleared, indicates that the Ethernet controller is not capable, or does
	not intend to stop upon reception of flow control Pause packets.
	Half-Duplex Ability
HD	When set, indicates that the Ethernet controller is capable of working in
	half-duplex mode of operation
	Full Duplex Ability
FD	When set, indicates that the Ethernet controller is capable of working in full-
	duplex mode of operation
RSV	Reserved
	Should be written as 0b

The reserved bits should be written as zero. The remote fault bits [13:12] can be set by software to indicate remote fault type to the link partner if desired. The AS and PS bits are used for advertisement of PAUSE frame operation. Refer to clause 37 of the 802.3z specification for details.

8.6.1.4Software Auto-Negotiation

Auto-Negotiation can also be performed by software with TXCW.ANE set to 0b. Data stored in the txConfigWord field is transmitted during the configuration process. Software should not (in general) read back the contents of this register.

If hardware loses receive synchronization, the contents of the TXCW register changes and during the time of the change, the value read back can be inconsistent. In the absence of loss of synchronization, the value read back is stable and equal to the last written value.

Software controls the negotiation process by writing the appropriate values to the txConfigWord and transmitting /C/ ordered sets by setting txConfig (in TXCW) to 1b. Software must monitor the RXCW register for status of the negotiation process and respond via writes to the TXCW register appropriately.

The software algorithm must follow the state machine implementation of sub-clause 37.3.1.5 of IEEE 802.3z, Figure 37-6. The link timer specification is 10 ms (+10 ms/-0 ms). In some systems, response time for the S/W implementation can make it difficult to meet this requirement if system utilization is high due to latencies on the PCI bus.

For more information, refer to the register definitions for TXCW and RXCW in Sections 13.4.13 and 13.4.14, respectively.

162 Software Developer’s Manual