Intel Intel Gigabit Ethernet Controllers, PCI-X manual Nlp

Register Descriptions

Table 13-31. PHY Specific Control Register Bit Description

Field	Bit(s)		Description		Mode	HW Rst	SW Rst
		1000BASE-T		10/100BASE-T
		Energy Detect.
Energy Detect	9:8	0xb = Off.			R/W	0b	Retain
		10b	= Sense only on receive.
		11b = Sense and periodically transmit
		NLP.
		1b = Force link good.
		0 b = Normal operation.
Force Link Good	10	If link is forced to be good, the link state			R/W	0b	Retain
		machine is bypassed and the link is
		always up. In 1000BASE-T mode this
		has no effect.
Assert CRS on		1b = Assert on transmit.
	11	0b = Never assert on transmit.			R/W	0b	Retain
Transmit
		This bit has no effect in full duplex.
		00b	= ± 16 Bits	00b = ± 8 Bits
		01b	= ± 24 Bits	01b = ± 12 Bits
Receive FIFO depth	13:12	10b	= ± 32 Bits	10b = ± 16 Bits	R/W	00b	Retain
		11b = ± 40 Bits		11b = ± 20 Bits
		Receive FIFO is enabled in internal
		SerDes mode2 or serial interface mode.
		00b	= ± 16 Bits	00 b= ± 8 Bits
		01b	= ± 24 Bits	01b = ± 12 Bits
Transmit FIFO depth	15:14	10b	= ± 32 Bits	10b = ± 16 Bits	R/W	00b	Retain
		11b = ± 40 Bits		11b = ± 20 Bits
		Transmit FIFO is enabled in 1000BASE-
		T mode or serial interface mode.

1.82544GC/EI only.

2.TBI Mode for the 82544GC/EI.

PHY Port Configuration Register (82541xx and 82547GI/EI Only)

PPCONF (16d; R/W)

Table 13-32. PHY Port Configuration Register Bit Description

Field	Bit(s)	Description	Mode	HW Rst	SW Rst
Reserved	0	Write to 0b for normal operation.	R/W	0b	0b
		1b = Enable alternate Auto-Negotiate
		next page feature.
Alternate NP Feature	1	0b = Disable alternate Auto-Negotiate	R/W	0b	0b
		next page feature.
		If polarity is disabled, then the polarity is
		forced to be normal in 10BASE-T.
Reserved	3:2	Write to 0b for normal operation.	R/W	0b	0b

Software Developer’s Manual 261