Intel Intel Gigabit Ethernet Controllers, PCI TX DMA Control 82544GC/EI only, Txdmac 03000h R/W

Register Descriptions

Table 13-84. TIDV Register Bit Description

31 16 15 0

Reserved

IDV

Field	Bit(s)	Initial		Description
		Value
IDV	15:0	X	Interrupt Delay Value
			Counts in units of 1.024	∝s. A value of 0bis not allowed.
Reserved	31:16	0b	Reserved
			Reads as 0b. Should be written to 0b for future compatibility.

13.4.42TX DMA Control (82544GC/EI only)

TXDMAC (03000h; R/W)

This register controls the transmit DMA pre-fetching and preemption abilities.

Table 11-85. TXDMAC Register Bit Description

31 1 0

Reserved

DPP

Field	Bit(s)		Initial	Description
			Value
				Disable packet prefetching
DPP	0	1		When set, prevents the Ethernet controller from starting a
				transmit descriptor data fetch before it has finished processing
				the previous descriptor. In general, performance increases
				when this bit is set to 0b.
Reserved	31:1	0		Reserved
				Reads as 0b. Should be written to 0b for future compatibility.

13.4.43Transmit Descriptor Control

TXDCTL (03828h; R/W)

This register controls the fetching and write back of transmit descriptors. The three threshold values provided are used to determine when descriptors are read from and written to host memory. The values can be in units of cache lines or descriptors (each descriptor is 16 bytes).

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