Intel Intel Gigabit Ethernet Controllers, PCI Signal Descriptions, Signal Ball Name and Function

General Initialization and Reset Operation

Note: IPGR1 and IPGR2 are not needed in full duplex, but are easier to always program to the values shown.

Table 14-1. Signal Descriptions

Signal	Ball	Name and Function
		Loss of Signal (TBI) / Link Indication. Loss of signal (high for lost
LOS / LINK	A10	signal) from the optical transceiver when LINK_MODE equals 11b;
		active high link indication from PHY in GMII/MII mode.
TX_DATA[9] / TX_ER	C7
	D7
TX_DATA[8] / TX_EN		Transmit Data.
	E6
TX_DATA[7]		TBI: TX_DATA[9:0] for transmit data bus.
	B5
TX_DATA[6]		GMII: TX_DATA[7:0] for transmit data bus.
	E5
TX_DATA[5]		TX_ER forces propagation of transmit errors and is used for carrier
TX_DATA[4]	C5	extension. TX_EN is asserted to indicate transmission of data on the
TX_DATA[3]	E4	interface.
TX_DATA[2]		MII: TX_DATA[3:0] for transmit data bus.
	C4
TX_DATA[1]		TX_ER is not used. TX_EN is used for transmit enable signal.
	D5
TX_DATA[0]
	D4
		Transmit Clock.
GTX_CLK	C6	TBI: 125 MHz transmit clock.
		GMII: Operates at 125 MHz.
		MII: Undefined.
		Enable Wrap.
		TBI: EWRAP is low in normal operation. When it is high, the SerDes
		device is forced to transceiver loopback the serialized transmit data
EWRAP	E10	to the receiver.
		This pin is tri-stated during EEPROM read. In order to avoid a
		floating input in an external SerDes, a weak external pull-down
		should be connected to this pin.
		GMII / MII: Not used.
		Collision.
		TBI: Undefined.
		GMII / MII: This signal indicates that a collision was detected on the
COL	E7	medium by the PHY. This signal remains asserted while the collision
		persists. For half-duplex transceivers, this signal indicates
		simultaneous transmission and reception. This signal is ignored in
		full-duplex mode.
		Normal Mode: This signal must be connected to VSS except for test
		mode.

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