Intel PCI-X, Intel Gigabit Ethernet Controllers manual Full Duplex, Half Duplex

Ethernet Interface

Configuration of the duplex operation of the Ethernet controller can be forced or determined via the Auto-Negotiation process. See Section 8.6 for details on link configuration setup and resolution.

8.4.1Full Duplex

All aspects of the IEEE 802.3, 802.3u, 802.3z, and 802.3ab specifications are supported in full duplex operation. Full duplex operation is enabled by several mechanisms depending on the speed configuration of the Ethernet controller and the specific capabilities of the PHY used in the application. During full duplex operation, the Ethernet controller may transmit and receive packets simultaneously across the link interface.

In Internal Serdes mode for the 82546GB/EB and 82545GM/EM (TBI mode for the 82544GC/ EI), the transmission and reception of packets is indicated by symbols embedded in the data stream. These symbols delineate the packet encapsulation and the protocol does not rely on other control signals. See Section 8.2.1.3 for details.

8.4.2Half Duplex

Note: The Ethernet controller operates in half duplex mode only when configured for internal PHY mode. For the 82546GB/EB and 82545GM/EM, internal SerDes mode does not support half duplex operation.

In half duplex mode, the Ethernet controller attempts to avoid contention with other traffic on the wire, by monitoring the carrier sense signal provided by the internal PHY, and deferring to passing traffic. When the Internal Carrier Sense signal is deasserted or after sufficient InterPacket Gap (IPG) has elapsed after a transmission, frame transmission can begin.

In the case of a collision, the internal PHY asserts a collision signal. Transmission of the frame stops within four clock times and then the Ethernet controller sends a JAM sequence onto the link. After the end of a collided transmission, the Ethernet controller backs off and attempts to retransmit per the standard CSMA/CD method. Note that the retransmission is done from the data stored internally in the Ethernet controller transmit packet buffer. The Ethernet controller does not access data in host memory again.

In the case of a successful transmission, the Ethernet controller is ready to transmit any other frames queued in its transmit FIFO within the minimum Inter Frame Spacing (IFS) of the link.

The internal carrier sense signal is expected to be asserted before one slot time has elapsed; however, the transmission completes successfully even if internal carrier sense is not asserted. If internal carrier sense is not asserted within the slot time window, the PHY is not behaving properly and can either be configured incorrectly or be in a link down situation. Note that this event is counted in the Transmit Without CRS statistic register (see Section 13.7.12).

Half duplex reception is as indicated for full duplex in Section 8.4.1 except for 1000 Mb/s specific operation, as described in Section 8.4.2.1 and Section 8.4.2.2.

The Ethernet controller does not provide support for half-duplex operation as specified in the IEEE 802.3z specification when operating at 1000 Mb/s in internal PHY mode.

Software Developer’s Manual 157