Intel PCI-X, Intel Gigabit Ethernet Controllers Capabilities Linked List, Address Next Pointer

PCI Local Bus Interface

Field	Bit(s)	Read/	Initial		Description
		Write	Value
				Indicates the address space where the CIS is
				located.
				0	= Configuration Space
				1	= BAR0
Space	2:0	R/W	0 or 2	2	= BAR1
				3	= BAR2
				4	= BAR3
				5	= BAR4
				6	= BAR5
				7	= Expansion ROM
				Offset within the specified address space,
				multiplied by eight. When enabled, the value
Offset	31:3	R	0 or 4	indicates that the CIS (Card Information
				Structure) is at an offset of 4*8, or 32 bytes into
				the Flash memory.

Subsystem ID	This value can be loaded automatically from the EEPROM upon power-up or
	PCI reset. A value of 1008h is the default for this field upon power-up if the
	EEPROM does not respond or is not programmed.

Subsystem Vendor ID

This value can be loaded automatically from the EEPROM upon power-up or

PCI reset. A value of 8086h is the default for this field upon power-up if the

EEPROM does not respond or is not programmed.

Cap_Ptr	The Capabilities Pointer field (Cap_Ptr) is an 8-bit field that provides an offset in
	the Ethernet controller’s PCI Configuration Space for the location of the first
	item in the Capabilities Linked List. The Ethernet controller sets this bit and then
	implements a capabilities list to indicate that it supports PCI Power
	Management, PCI-X, and Message Signaled Interrupts1. Its value is DCh which
	is the address of the first entry: ACPI2 Power Management.
	Address	Item	Next Pointer
	DCh-E0h	ACPI Power Management	E4h
	E4h-E8h	PCI-X	F0h
	F0h-FCh	Message Signaled Interrupt	00h

Figure 4-1. Capabilities Linked List

In conventional PCI mode, Message Signaled interrupts can be disabled in the EEPROM. If disabled, the message signaled interrupts won’t appear on the linked list and PCI-X’s “Next Pointer” is 0b.

1.Not applicable to the 82541xx or 82547GI/EI.

2.Not applicable to the 82541ER.

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