Intel PCI-X, Intel Gigabit Ethernet Controllers manual Software Developer’s Manual 263

Register Descriptions

13.4.7.1.14PHY Specific Status Register PSSTAT (17d; R)

Table 13-33. PHY Specific Status Register Bit Description

Field	Bit(s)		Description	Mode	HW Rst	SW Rst
Jabber (real time)	0	1b	= Jabber.	RO	0b	Retain
		0 = No jabber.
Polarity (real time)	1	1b	= Reversed.	RO	0b	0b
		0b	= Normal.
		1b	= Receive pause enabled.
		0b	= Receive pause disabled.
		The Receive Pause Enable bit is valid
Receive Pause	2	only after the Speed and Duplex		RO	0b	0b
		Resolved bit (11) is set. This occurs
Enable
		when Auto-Negotiation is completed or
		Auto-Negotiation is disabled.
		This is a reflection of the MAC pause
		resolution.
		1b	= Transmit pause enabled.
		0b	= Transmit pause disabled.
Transmit Pause	3	The Transmit Pause Enable bit is valid		RO	0b	0b
		only after the Speed and Duplex
Enabled
		Resolved bit (11) is set. This occurs
		when Auto-Negotiation is completed or
		Auto-Negotiation is disabled.
Energy Detect Status	4	0b	= Active	RO	0b	0b
		1b	= Sleep
Downshift Status	5	1b	= Downshift.	RO	0b	0b
		0b	= No Downshift.
		1b	= MDI-X.
		0b	= MDI.
MDI Crossover	6	The MDI Crossover Status bit is valid		RO	0b	0b
		only after the Speed and Duplex
Status
		Resolved bit (11) is set. This occurs
		when Auto-Negotiation is completed or
		Auto-Negotiation is disabled.
		000b = < 50 m.
		001b = 50 − 80 m.
		010b = 80 − 110 m.
Cable Length		011b = 110 − 140 m.
	9:7	100b = >140 m.		RO	000b	000b
(100/1000 modes
		Cable length measurement is only a
only)
		rough estimate. The actual value
		depends on the attenuation of the cable,
		output levels of the remote transceiver,
		connector impedance, etc.
Link (real time)	10	1b	= Link up.	RO	0b	0b
		0b	= Link down.

Software Developer’s Manual 263