Intel Intel Gigabit Ethernet Controllers, PCI 4 10/100/1000 Mb/s Receive and Transmit MAC Blocks

Architectural Overview

•Offloading the receiving and transmitting IP and TCP/UDP checksums

•Directly retransmitting from the transmit FIFO any transmissions resulting in errors (collision detection, data underrun), thus eliminating the need to re-access this data from host memory

2.3.410/100/1000 Mb/s Receive and Transmit MAC Blocks

The controller’s CSMA/CD unit handles all the IEEE 802.3 receive and transmit MAC functions while interfacing between the DMA and TBI/internal SerDes/MII/GMII interface block. The CSMA/CD unit supports IEEE 802.3 for 10 Mb/s, IEEE 802.3u for 100 Mb/s and IEEE 802.3z and IEEE 802.3ab for 1000 Mb/s.

The Ethernet controller supports half-duplex 10/100 Mb/s MII or 1000 Mb/s GMII mode and all aspects of the above specifications in full-duplex operation. In half-duplex mode, the Ethernet controller supports operation as specified in IEEE 802.3z specification. In the receive path, the Ethernet controller supports carrier extended packets and packets generated during packet bursting operation. The 82554GC/EI, in the transmit path, also supports carrier extended packets and can be configured to transmit in packet burst mode.

The Ethernet controller offers various filtering capabilities that provide better performance and lower processor utilization as follows:

•Provides up to 16 addresses for exact match unicast/multicast address filtering.

•Provides multicast address filtering based on 4096 bit vectors. Promiscuous unicast and promiscuous multicast filtering are supported as well.

•The Ethernet controller strips IEEE 802.1q VLAN tag and filter packets based on their VLAN ID. Up to 4096 VLAN tags are supported1.

In the transmit path, the Ethernet controller supports insertion of VLAN tag information, on a packet-by-packet basis.

The Ethernet controller implements the flow control function as defined in IEEE 802.3x, as well as specific operation of asymmetrical flow control as defined by IEEE 802.3z. The Ethernet controller also provides external pins for controlling the flow control function through external logic.

2.3.5MII/GMII/TBI/Internal SerDes Interface Block

The Ethernet controller provides the following serial interfaces:

•A GMII/MII interface to the internal PHY.

•Internal SerDes interface2 (82546GB/EB and 82545GM/EM)/Ten Bit Interface (TBI)2 for the 82544GC/EI: The Ethernet controller implements the 802.3z PCS function, the Auto- Negotiation function and 10-bit data path interface (TBI) for both receive and transmit operations. It is used for 1000BASE-SX, -LX, and -CX configurations, operating only at 1000 Mb/s full-duplex. The on-chip PCS circuitry is only used when the link interface is configured for TBI mode and it is bypassed in internal PHY modes.

1.Not applicable to the 82541ER.

2.Not applicable to the 82544GC/EI, 82540EP/EM, 82541xx, and 82547GI/EI.

12 Software Developer’s Manual