Power Management

6.3.3.4Power Management Control / Status Register - (PMCSR) 2 Bytes Offset = 4 (RO)

Bits

Default

R/W

Description

 

 

 

 

 

 

 

PME_Status – This bit is set when the function would normally assert the

 

 

 

PME# signal independent of the state of the PME_En bit. The Ethernet

 

 

Read/

controller returns a value of 1b for this bit if a Wakeup condition has been

 

0b (see

detected.

15

Write 1b

Writing a 1b clears this bit and deasserts PME#a.

description)

 

 

to clear

If the AUX_POWER input is 1b, the PME_Status field is only reset by

 

 

 

 

 

 

LAN_PWR_GOOD. If AUX_POWER is 0b, PME_Status is also reset on the

 

 

 

deassertion (rising edge) of RST#.

 

 

 

 

 

00b

 

Data_Scale - This 2- bit read-only field indicates the scaling factor to be

 

01b if

Read

used when interpreting the value of the Data register. This field outputs 01b

14:13

Manageability is

(to indicate units of 0.1 watt) when Manageability is enabled in the

Only

 

enabled

EEPROM and the Data_Select field is set to 0, 3, 4, or 7, and 00b

 

 

 

(see description)

 

otherwise.

 

 

 

 

 

 

 

 

 

Read/

Data_Select - This 4-bit field is used to select which data is to be reported

12:09

0000b

through the Data register and Data_Scale field. These bits are only writable

Write

 

 

when Power Management is enabled via EEPROM.

 

 

 

 

 

 

 

 

 

 

PME_En – If Power Management is not disabled in the EEPROM, writing a

 

 

 

1b to this register enables Wakeup and causes the Ethernet controller to

 

 

 

assert PME# when it receives a Wakeup event enabled in the Wakeup Filter

 

 

 

Control Register (WUFC).

 

 

 

Note: This bit cannot be set for the 82541ER.

08

0b on Power-On

Read/

If Power Management is disabled in the EEPROM, writing a 1b to this bit

reset

Write

has no affect, and does not set the bit to 1b.

 

 

 

 

If the AUX_POWER input is 1b, the PME_En field is only reset by

 

 

 

LAN_PWR_GOOD. If AUX_POWER is 0b, it is also reset on the

 

 

 

deassertion (rising edge) of RST#.

 

 

 

Note: If APM Wakeup is enabled, the PME# pin can be asserted even if

 

 

 

PME_En is 0b. See Section 6.4.1 for details.

 

 

 

 

07:02

000000b

Read

Reserved - The Ethernet controller returns a value of 000000b for this field.

Only

 

 

 

 

 

 

 

 

 

 

PowerState - This 2-bit field is used both to determine the current power

 

 

 

state of a function and to set the function into a new power state. The

 

 

 

definition of the field values is as follows:

 

 

 

00b - D0

 

 

 

01b - D1 (ignored if written with this value)

01:00

00b

Read/

10b - D2 (ignored if written with this value)

11b - D3

Write

 

 

 

 

 

If software attempts to write an unsupported state to this field, 00b or 10b, or

 

 

 

if Power Management is disabled in the EEPROM, then the Ethernet

 

 

 

controller completes the write operation normally on the bus, however the

 

 

 

data is discarded and no state change occurs.

 

 

 

These bits are cleared and the power state is returned to D0 after the trailing

 

 

 

edge of RST#.

 

 

 

 

a.Not applicable to the 82541ER.

This register is used to control and monitor power management events in the Ethernet controller. If auxiliary power is present, as indicated by AUX_POWER = 1b, a PCI reset does not clear PME_En and PME_Status.

Software Developer’s Manual

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Intel PCI-X, Intel Gigabit Ethernet Controllers manual Software Developer’s Manual 139