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Intel Intel Gigabit Ethernet Controllers, PCI-X manual Eeprom Interface, General Overview

Models: Intel Gigabit Ethernet Controllers PCI-X PCI

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	EEPROM Interface
EEPROM Interface	5

5.1General Overview

The PCI/PCI-X Family of Gigabit Ethernet Controllers uses an EEPROM device for storing product configuration information. The EEPROM is divided into four general regions:

•Hardware accessed – loaded by the Ethernet controller after power-up, PCI Reset deassertion, D3->D0 transition, or software commanded EEPROM reset (CTRL_EXT.EE_RST).

•ASF accessed – loaded by the Ethernet controller in ASF mode after power-up, ASF Soft Reset (ASF FRC_RST), or software commanded ASF EEPROM read (ASF FRC_EELD).

•Software accessed – used by software only. The meaning of these registers as listed here is a convention for the software only and is ignored by the Ethernet controller.

•External BMC (TCO) accessed – loaded by an external BMC (TCO) from the SMBus after power up.

Note: The 82544GC/EI and 82541ER do not support ASF, SMBus, or an external BMC (TCO).

Several words of the EEPROM are accessed automatically by the Ethernet controller after reset to provide pre-boot configuration data before it is accessed by host software. The remainder of the stored information is available to software for storing the MAC address, serial numbers, and additional configuration information.

Intel has a software utility called EEUPDATE, which can be used to program EEPROM images in development or production line environments. To obtain a copy of this program, contact your Intel representative.

Note: Since the 82546GB/EB is a dual port device, there are portions of the EEPROM and Flash that control one or both ports. Special considerations due to this feature are noted in this section.

Software Developer’s Manual

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Intel Intel Gigabit Ethernet Controllers, PCI-X manual Eeprom Interface, General Overview

Contents

82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, Software Developer’s Manual Initial Public Release Date Version CommentsSoftware Developer’s Manual Contents TCP Segmentation Use of Multiple Data Descriptors Software Developer’s Manual Vii Power Management 129 Introduction to Power Management 10.1.3 203 13.4.25 13.7.10 Appendix 82540EP/EM and 82545GM/EM Differences Xiv Overview ScopeNetwork Side Features Ethernet Controller FeaturesPCI Features CSA Features 82547GI/EI OnlyHost Offloading Features Additional Performance Features Technology Features Additional Ethernet Controller FeaturesRegister and Bit References ConventionsRelated Documents Memory Alignment TerminologyIntroduction Architectural OverviewLAN a LAN B External ArchitecturePHY AGC, A/D Eeprom FlashECHO, Next Fext 1 PCI/PCI-X Core Interface MicroarchitectureDMA Engine and Data Fifo 2 82547GI/EI CSA Interface5 MII/GMII/TBI/Internal SerDes Interface Block 4 10/100/1000 Mb/s Receive and Transmit MAC BlocksEeprom Interface 6 10/100/1000 Ethernet Transceiver PHYLittle Endian Data Ordering DMA AddressingFlash Memory Interface Example 2-1. Byte OrderingIA Byte # LSB MSB Ethernet AddressingIntel Architecture Byte Ordering Interrupts TCP Segmentation Hardware Acceleration CapabilityBuffer and Descriptor Structure Checksum OffloadingArchitectural Overview Packet Address Filtering IntroductionPacket Reception Receive Descriptor Rdesc Layout Receive Data StorageReceive Descriptor Format Receive Receive Descriptor Status FieldReceive Status RDESC.STATUS Layout PIF Ipcs Tcpcs RSV Ixsm EOPReceive Descriptor Errors Field CXE Receive Errors RDESC.ERRORS LayoutRXE IPE Tcpe RSV RSV SEQPRI Receive Descriptor Special FieldSpecial Descriptor Field Layout PRI CFI VlanReceive Descriptor Fetching Algorithm Receive Descriptor FetchingNull Descriptor Padding Receive Descriptor Write-BackReceive Descriptor Queue Structure Receive Descriptor PackingReceive Descriptor Ring Structure Receive Interrupts Receive Timer InterruptReceive Interrupt Delay Timer / Packet Timer Rdtr Packet Delay Timer Operation State Diagram Receive Interrupt Absolute Delay Timer RadvSmall Receive Packet Detect Receiver Fifo Overrun 8 82544GC/EI Receive InterruptsReceive Packet Checksum Offloading Receive Descriptor Minimum Threshold ICR.RXDMTPacket Type HW IP Checksum HW TCP/UDP Checksum Calculation Supported Receive Checksum CapabilitiesPacket Type HW IP Checksum MAC Address FilterGC/EI Supported Receive Checksum Capabilities Packet Type HW IP Checksum HW TCP/UDP Checksum9.4 IPv6 Filter Packet TransmissionSNAP/VLAN Filter 9.3 IPv4 FilterTransmit Descriptors Transmit Data StorageTransmit Descriptor Legacy Descriptions Transmit Descriptor Tdesc Layout Legacy ModeLegacy Transmit Descriptor Format Transmit Descriptor Tdesc LayoutCSS Transmit Descriptor Description LegacyCMD STAIfcs EOP Transmit Descriptor Command Field Format10. Transmit Command TDESC.CMD Layout IDE VLE Dext RSV11. Transmit Status Layout Transmit Descriptor Status Field Format12. Special Field TDESC.SPECIAL Layout Transmit Descriptor Special Field Format5 TCP/IP Context Transmit Descriptor Format 13. Transmit Descriptor Tdesc Layout Type = 0000b 6 TCP/IP Context Descriptor LayoutTransmit Description Descriptor Offload 14. Transmit Descriptor Tdesc LayoutDtyp 6.1 TCP/UDP Offload Transmit Descriptor Command FieldTransmit Description Tucmd82544GC/EI only 15. Command Field TDESC.TUCMD LayoutIDE RSV Dext TSE TCP 16. Transmit Status Layout 7 TCP/IP Data Descriptor Format6.2 TCP/UDP Offload Transmit Descriptor Status Field Popts 17. Transmit Descriptor Tdesc Layout Type = 0001bPopts RSV STA Dcmd Dtyp Dtalen TSE Ifcs EOP 7.1 TCP/IP Data Descriptor Command Field18. Command Field TDESC.DCMD Layout IDE VLE DextReserved 7.2 TCP/IP Data Descriptor Status Field19. Transmit Status Layout RSV Txsm Ixsm 7.3 TCP/IP Data Descriptor Option Field7.4 TCP/IP Data Descriptor Special Field 20. Packet Options Field TDESC.POPTS Layout21. Special Field TDESC.SPECIAL Layout Transmit Descriptor Ring StructureTransmit Descriptor Ring Structure Transmit Descriptor Write-back Transmit Descriptor FetchingTransmit Interrupts Delayed Transmit Interrupts Transmission Process AssumptionsTCP/UDP Data FCS TCP Segmentation PerformancePacket Format TCP Segmentation Data Fetch Control3936 TCP Segmentation IndicationTCP Partial Pseudo-Header Checksum TCP Segmentation Use of Multiple Data DescriptorsOptions IP and TCP/UDP HeadersVersion IP Hdr Offset High Header Checksum Type of service Version IP Hdr Length FragmentFragment Offset Low Byte1 Byte0 Destination Port Destination Port Sequence NumberTCP Header Length Checksum Urgent Pointer OptionsByte3 Byte2 Byte1 Byte0 Source Port Destination Port Length ChecksumTransmit Checksum Offloading with TCP Segmentation 17. UDP Pseudo Header Diagram for IPv49 IP/TCP/UDP Header Updating 19. Overall Data Flow 9.2 TCP/IP/UDP Header for the Subsequent Frames 9.1 TCP/IP/UDP Header for the First Frame9.3 TCP/IP/UDP Header for the Last Frame IP/TCP/UDP Transmit Checksum OffloadingIpcss Receive and Transmit Description PCI PCI ConfigurationMandatory PCI Registers Address DescriptionSpecification Update for the latest stepping information Addr Base Address RegistersField Bits Read Initial Description Write Value All base address registers have the following fieldsOffset Space Expansion ROM Base AddressAddress Next Pointer Capabilities Linked ListBits Initial Value Description PCI definition for more details82547GI/EI Status Register LayoutByte Offset PCI-X Configuration RegistersPCI-X Capability ID Next CapabilityMaximum Memory Read Byte Count. This register sets PCI-X CommandBits Read Initial Write ValueBits Read Intial Description Write Value PCI-X StatusUSC SCD Reserved and Undefined Addresses Command Register as followsBits Read Initial Description Write Value 05h Message Signaled Interrupts1Message Signaled Interrupt Configuration Registers MSI Capability IDMessage Control 3.1.6 Commands3.1.4 Message Address 3.1.5 Message Upper AddressTransaction Cause PCI Commands PCI-X Commands Accepted PCI/PCI-X Command as a TargetPCI Commands Abr PCI-X Commands Transaction Target PCI Commands PCI-X CommandsMemory Write Operations PCI/PCI-X Command UsageMWI Bursts Master Write Command Usage AlgorithmRules for Memory Read Operations PCI-X Command UsageMemory Read Operations MW BurstsOutstanding Memory Read Cache Line Information1Target Transaction Termination LAN DisableInterrupt Assignment 82547GI/EI Only CardBus Application 82541PI/GI/EI Only General Overview Eeprom InterfaceStepping Vendor ID Device ID Description Component Identification Via Programming InterfaceComponent Identification Eeprom Device and Interface Signature and CRC Fields Software AccessCommand Line Parameters Eeupdate UtilityFor the 82541xx and 82547GI Eeprom Address Map1Ethernet Controller Address Map Word Used Bit Image82546GB/EB only LAN a82545GM 82540EP 82541xx and 82547GI/EI only82545GM 82541xxASF 82540EP/EMAddress Hi Byte Low Byte Word Description Default HW AccessGC/EI and 82541ER Eeprom Address Map Bit Name Description Ethernet Address Words 00h-02hSoftware Compatibility Word Word 03h Software Compatibility Word Word 03hPBA Number Word 08h, 09h SerDes Configuration Word 04hEeprom Image Version Word 05h Compatibility Fields Word 05h 07hInitialization Control Word 1 Word 0Ah Initialization Control Word 1 Word 0AhSubsystem Vendor ID Word 0Ch Subsystem ID Word 0BhInitialization Control Word 2 Word 0Fh Device ID Word 0Dh, 11h1Vendor ID Word 0Eh Initialization Control Word 2 Word 0Fh82541PI/GI Only OEM Reserved Words Words 10h, 11h, 13h 1Fh Common Power Word 12hSoftware Defined Pins Control Word 10h1, 20h PHY Register Address Data Words 10h, 11h, and 13h 1EhSoftware Defined Pins Control Word 10h, 20h Bit Description Default CSA Port Configuration 2 Word 21hCSA Port Configuration 2 Word 21h Reserved Words 23h 2Eh 20 D0 Power Word 22h high byte21 D3 Power Word 22h low byte Circuit Control Word 21h82541PI/GI/EI and 82547GI/EI Only 10. Initial Management Control Register SettingsManagement Control Word 13h1, 23h2 11. SMBus Slave Address SMBus Slave Address Word 14h1 low byte, 24h low byteFor Address 24h High Byte / LAN a Initialization Control 3 Word 14h1 high byte, 24h high byte12. Initialization Control 82546GB/EB uses INTB#28 IPv6 Address words 17h 1Eh1 and 27h 2Eh LED Configuration Defaults Word 2Fh2Boot Agent Main Setup Options Word 30h 27 IPv4 Address Words 15h 16h1 and 25h 26h15. Boot Agent Main Setup Options BBS Boot Agent Configuration Customization Options Word 31hDBS DFU 16. Boot Agent Configuration Customization Options Word 31hSIG Mode17. Boot Agent Configuration Customization Options Word 32h Boot Agent Configuration Customization Options Word 32h18. IBA Capabilities IBA Secondary Port Configuration Words 34h-35hIBA Capabilities Word 33h Eeprom Images 19. WOL Mode and Functionality Word 0Ah20. WOL Mode and Functionality Word 20h Checksum Word Calculation Word 3FhNumber Parallel Flash Memory21. Flash Memory Manufacturers Manufacturer124 Flash Interface Operation Flash Control and AccessesWrite Accesses Read AccessesFlash Buffer Write Cycle 128 Assumptions Introduction to Power ManagementD3cold support Power States1.2 D0u State Dr State1.4 D3 Timing1.3 D0a D0 active Diagram # Power Up Off to Dr to D0u to D0aTransition from D0a to D3 and Back Without PCI Reset Transition From D0a to D3 and Back Without PCI ResetRST# Transition From D0a to D3 and Back with PCI ResetPCI Reset Sequence PCI Reset Without Transition to D3Next Item Pointer Byte Offset = 1 RO PCI Power Management RegistersBits Default Description Capability ID Byte Offset = 0 ROEeprom Power Management Capabilities PMC 2 Bytes Offset = 2 ROReserved Software Developer’s Manual 139 Byte Offset = 7 RO Pmcsrbse Bridge Support Extensions3.6 Data Register Byte Offset = 6 ROWakeup Advanced Power Management WakeupAcpi Power Management Wakeup Directed Exact Packet Wakeup PacketsPre-Defined Filters Offset Field Value Action Comment 3.1.3 BroadcastDirected Multicast Packet 3.1.4 Magic Packet*1Offset Field Value Action Comment Bytes ARP 3.1.5 ARP/IPv4 Request Packet1+ S a + D + S aOffset # of bytes Field Value Action Comment Directed IPv4 Packet1Directed IPv6 Packet1 + D + S IPX Diagnostic Responder Request Packet Example1Flexible Filter + S3.4 IPv6 Neighbor Discovery Filter1 Directed IPX Packet ExampleCRC Wakeup Packet Storage152 Link Interfaces Overview Ethernet Interface1.2 8B10B Encoding/Decoding Internal SerDes Interface/TBI Mode- 1Gb/s1Code OrderedSet Gmii 1 Gb/sCode Groups and Ordered Sets Code Group and Ordered Set UsageMII 10/100 Mb/s Internal Interface1Duplex Operation Half Duplex Full DuplexPacket Bursting Carrier Extension 1000 Mb/s OnlyAuto-Negotiation and Link Setup2 Auto-Negotiation and Link Setup1Auto-Negotiation Link Configuration in Internal Serdes/TBI Mode1Link Speed Hardware Auto-Negotiation TXCW.txConfigWordBit Description Software Auto-NegotiationForcing Link Internal GMII/MII ModeForcing Speed Using Auto-Speed Detection ASDComments Regarding Forcing Link Automatic Detection of Link Speed using SPD-INDDuplex MII Management RegistersControl Bit Effect on Control Bits Internal SerDes Mode1 Control Bit ResolutionInternal Serdes Mode1 Hardware Enabled Internal Serdes1 Mode Software EnabledInternal Serdes Mode1 Auto-Negotiation Skipped Internal PHY Mode Control Bit ResolutionGMII/MII Mode PHY Speed Indication GMII/MII Mode Force Speed GMII/MII Mode Auto-Speed DetectionGMII/MII Mode Force Link Loss of Signal/Link Status IndicationInternal Serdes Mode Internal PHY ModeAdaptive IFS1 10/100 Mb/s Specific Performance EnhancementsRegister Name Description Flow ControlMAC Control Frames & Reception of Flow Control Packets 10. Flow Control Registers3x MAC Control Frame Format Transmission of Pause Frames Discard Pause Frames and Pass MAC Control FramesExternal Control of Flow Control Operation1 Software Initiated Pause Frame TransmissionPacket #Octets 802.1q Vlan Packet Format1 802.1q Tagged Frames Vlan Packet Format ComparisonStripping 802.1q Tags on Receives Transmitting and Receiving 802.1q Packets802.1q Vlan Packet Filtering Adding 802.1q Tags on TransmitsVFE Packet Reception Decision Table178 Selecting an LED Output Source Configurable LED Outputs1Blink Control Polarity InversionBlink Control 182 Auto-Negotiation PHY Functionality and FeaturesNext Page Exchanges Register Update1000BASE-T 11.2 MDI/MDI-X Crossover copper onlyStatus Pin11.2.2 10/100 Downshift 82540EP/EM Only Polarity Correction copper onlyLink Down Energy Detect copper only PHY Power Management copper onlyCable Length Detection copper only 11.4.2 D3 State, No Link Required copper only 11.4.3 D3 Link-Up, Speed-Management Enabled copper only11.4.4 D3 Link-Up, Speed-Management Disabled copper only Initialization Mdio Control ModeOverview of Link Establishment Determining Link StateDetermining Duplex State Via Parallel Detection Configuration ResultFalse Link Forced Operation11.7.1 1000BASE-T Link CriteriaAuto Negotiation Parallel DetectionSmartSpeed Using SmartSpeedLink Enhancements 11.7.3 10BASE-TManagement Data Interface Low Power OperationPause And Asymmetric Pause Settings Asmdir Settings Pause Setting11.11 1000 Mbps Operation Powerdown via the PHY RegisterSmart Power-Down DSP ECHO, Next 4DPAM5 Transmit Fifo Transmit FunctionsTransmit/Receive Flow Spectral ShaperLow-Pass Filter Line DriverReceive Functions Viterbi Decoder/Decision Feedback Equalizer DFE 11.12 100 Mbps Operation11.13 10 Mbps Operation DescramblerPHY Line Length Indication 202 12.2.1 PCI/PCI-X interface Features of Each MACIntroduction1 204 IO BAR MAC Configuration Register Space12.2.3 SDP, LED, INT# output Eeprom Arbitration Shared EepromEeprom Map Shared Flash Flash Access ContentionPin sampled LAN device controlled Enable/Disable Values Sampled on ResetInterrupt Use Power ReportingMulti-Function Advertisement INTA# EnabledSummary Interrupt Line UsedRegister Conventions Register DescriptionsMemory and I/O Address Decoding Memory-Mapped Access to Internal Registers and MemoriesMemory-Mapped Access to Flash Memory-Mapped Access to Expansion ROMIoaddr IoaddrIodata Offset Abbreviation Name SizeAD C/BE#30 Bits Iodata Register Configurations82547GI/EI only Ethernet Controller Register SummaryCategory Offset Abbreviation Name 82544GC/EIIpat 82544GC Gprc XofftxcFcruc PRC64To the 82544GC/EI , 82541xx , or 82547GI CategoryAbbreviation Name Register 82544GC/EI , 82541xx , or 82547GI/EIPCI-X Register Access Split1 Ctrl 00000h R/W Main Register DescriptionsDevice Control Register Field Bits Initial Description Value Ctrl Register Bit DescriptionSpeed SLUIlos ADVD3WUC FrcdplxSDP0DATA SDP1DATAField Bits Initial Description Little-Endian Data Ordering BEM = 0 64-bit mode Little-EndianDevice Status Register Status 00008h RTbimode Status Register Bit DescriptionTxoff Pcixspd AsdvPCI66 Pcixmode82544GC/EI Only EEPROM/Flash Control & Data RegisterEecd 00010h R/W Eecd Register Bit DescriptionEesize EereqEegnt EepresEeprom Read Register Bit Description Eeprom Read Register1Eerd 00014h RW Done Start Eeprom Read Register Bit Description 82541xx and 82547GI/EIFLA 0001Ch R/W Flash Access1Flash Access FLA 23 16 Extended Device Control RegisterCtrlext 00018h, R/W 10. Ctrlext Register Bit DescriptionAsdchk SDP6IODIRSDP2IODIR SDP7IODIRLinkmode Vreg Power11. GPI to SDP Bit Mappings DownCTRL.RST Swdpinshi12 GC/EI Ctrlext Register Bit Description Swdpiohi13 GC/EI GPI to SDP Bit Mapping Mdic 00020h R/W MDI Control RegisterPhyadd 14. MDI Control Register Bit DescriptionRSV PHY REG Data RegaddPHY Registers 15. PHY Register Bit Mode DefinitionsRegister Mode Description MSB Field Bits Description Mode HW Rst SW Rst242 LSB EnaxcRO,L Software Developer’s Manual 245 246 For the 82541xx and 82547GI/EI Pause 82544GC/EI only 82541xx82541xx 82547GI/EI 82541xx and 82547GI/EI only RF1 82544GC/EI OnlyANEG3 ANEG2Software Developer’s Manual 251 23. Link Partner Ability Register Base Page Bit Description1 100BASE-TX 82541xx and 82547GI/EI Only24. PHY Link Page Ability Bit Description1 10BASE-T1b 82541xx Software Developer’s Manual 255 Bits Field Description Mode HW Rst SW Rst ANEG1 MasterANEG0 MASTER/SLAVE258 Software Developer’s Manual 259 DIS NLP SFD PreenSoftware Developer’s Manual 263 264 Software Developer’s Manual 265 266 82541/GI/ER and 82547GI B1 82541EI/82547GI B0 stepping268 HCD NOK Software Developer’s Manual 271 272 Field Bits Description Mode HW Rst Ledactled SPEED1000LED SPEED100LED276 Software Developer’s Manual 277 To Perform Operation MDI Read/Write Sequence Documented MDI Register 30 Operations151. MDI Register 30 Operations Fcah 0002Ch R/W Flow Control Address LowFlow Control Address High Fcal 00028h R/WVET 00038h R/W Flow Control TypeVlan Ether Type FCT 00030h R/W57. Fcttv Register Bit Description Flow Control Transmit Timer ValueFcttv 00170h R/W 56. VET Register Bit Description58. Txcw Register Bit Description Transmit Configuration Word Register1Txcw 00178h R/W Rxcw 00180h R Receive Configuration Word Register159. Rxcw Register Bit Description LED1 ACTIVITY# LED0 LINKUP# LED Control1Ledctl 00E00h RW ANC60. LED Control Bit Description1 Mode Encodings for LED Outputs1Mode Pneumonic State / Event Indicated 61. Mode Encodings for LED OutputsField Bits Initial Value Description Packet Buffer AllocationPBA 01000H R/W 62. PBA Register Bit Description63. ICR Register Bit Description Interrupt Cause Read RegisterICR 000C0H R GPISDP6 RXT0Mdac RxcfgInterval Interrupt Throttling Register1ITR 000C4h R/W 64. ICS Register Bit Description Interrupt Cause Set RegisterICS 000C8h W To the 82544GC/EI Interrupt Mask Set/Read RegisterIMS 000D0h R/W 65. IMS Register Bit DescriptionIMC 000D8h W Interrupt Mask Clear Register66. IMC Register Bit Description SBP Receive Control RegisterRctl 00100h R/W 67. Rctl Register Bit DescriptionRdmts MPELPE LBMCfien BAMBsize VFESecrc PmcfBsex 68. Fcrtl Register Bit Description XON Enable 82544GC/EI , 82541xx , and 82547GI/EI onlyFlow Control Receive Threshold Low Fcrtl 02160h R/W69. Fcrth Register Bit Description Flow Control Receive Threshold HighFcrth 02168h R/W Rdbah 02804h R/W Receive Descriptor Base Address LowReceive Descriptor Base Address High Rdbal 02800hR/WRDH 02810h R/W Receive Descriptor LengthReceive Descriptor Head Rdlen 02808h R/WRdtr 02820h R/W Receive Delay Timer RegisterReceive Descriptor Tail RDT 02818hR/WRadv 0282Ch RW Receive Interrupt Absolute Delay Timer1Tctl 00400hR/W Receive Small Packet Detect Interrupt1Transmit Control Register Rsrpd 02C00h R/WTCTL.COLD 76. Tctl Register Bit DescriptionCold PSPNrtu Transmit IPG RegisterTipg 00410R/W RtlcIPGR2 IPGR1 Ipgt 77. Tipg Register Bit DescriptionIPGR2 Adaptive IFS Throttle AITAifs 00458R/W 79. Tdbal Register Bit Description Transmit Descriptor Base Address LowTdbal 03800h R/W 78. Aifs Register Bit DescriptionTdlen 03808h R/W Transmit Descriptor Base Address HighTransmit Descriptor Length Tdbah 03804h R/W82. TDH Register Bit Description Transmit Descriptor HeadTDH 03810h R/W Tidv 03820h R/W Transmit Interrupt Delay ValueTransmit Descriptor Tail TDT 03818h R/WTxdctl 03828h R/W TX DMA Control 82544GC/EI onlyTransmit Descriptor Control Txdmac 03000h R/WLwthresh RSV1 Gran RSV Wthresh Hthresh Pthresh 86. Txdctl Register Bit DescriptionLwthresh Transmit Absolute Interrupt Delay Value1Tadv 0382Ch RW GranTspbp TCP Segmentation Pad And Minimum Threshold Tspmt 03830h RWTspbp Tsmt Software Developer’s Manual 319 Wthresh RSV Hthresh Pthresh Receive Descriptor ControlRxdctl 02828h R/W 87. Rxdctl Register Bit Description3111 Receive Checksum ControlRxcsum 05000h R/W 88. Rxcsum Register Bit DescriptionIPV6OFL IpofldTuofld 89. MTA Register Bit Description Filter RegistersMulticast Table Array MTA1270 05200h-053FCh R/WDestination Address RAH 05404h + 8∗n R/W Receive Address LowReceive Address High RAL 05400h + 8*n R/WRAH Vlan Filter Table Array1VFTA1270 05600h 057FCh R/W 91. RAH Register Bit Description92. VFTA1270 Bit Description Wakeup RegistersWakeup Control Register WUC 05800h R/WSPM Wakeup Filter Control RegisterWufc 05808h R/W ApmpmeWUS 05810h R Wakeup Status Register330 Ipav 5838h R/W IP Address ValidField Dword # Address Bits Initial Value Description 13.6.5 IPv4 AddressIP4AT 05840h 05858h R/W2 AddressDword # Address Bits Initial Value Description 13.6.6 IPv6 AddressIP6AT 05880h 0588Ch R/W IPV6ADDR0Flexible Filter Length Table Wakeup Packet LengthWakeup Packet Memory 128 Bytes LEN2 Flexible Filter Mask Table Ffmt 09000h 093F8h R/WLEN0 LEN1Ffvt 09800h 09BF8h R/W Statistics RegistersFlexible Filter Value Table Algnerrc 04004h R CRC Error CountAlignment Error Count Crcerrs 04000h RRxerrc 0400Ch R Symbol Error CountRX Error Count Symerrs 04008h RSCC 04014h R Missed Packets CountSingle Collision Count MPC 04010h RMCC 0401Ch R Excessive Collisions CountMultiple Collision Count Ecol 04018h RColc 04028h R Late Collisions CountCollision Count Latecol 04020h RTncrs 04034h R Defer CountTransmit with No CRS DC 04030h RCexterr 0403Ch R Sequence Error CountCarrier Extension Error Count SEC 04038h RXonrxc 04048h R Receive Length Error CountXON Received Count Rlec 04040h RXoff Transmitted Count XON Transmitted CountXoff Received Count PRC64 0405Ch R FC Received Unsupported CountPackets Received 64 Bytes Count Fcruc 04058h RPRC255 04064h R Packets Received 65-127 Bytes CountPackets Received 128-255 Bytes Count PRC127 04060h RPRC1023 0406Ch R Packets Received 256-511 Bytes CountPackets Received 512-1023 Bytes Count PRC511 04068h RGprc 04074h R Packets Received 1024 to Max Bytes CountGood Packets Received Count PRC1522 04070h RMprc 0407Ch R Broadcast Packets Received CountMulticast Packets Received Count Bprc 04078h RGorcl 04088h R/GORCH 0408Ch R Good Packets Transmitted CountGood Octets Received Count Gptc 04080h RRnbc 040A0h R Good Octets Transmitted CountReceive No Buffers Count Gotcl 04090h R/ Gotch 04094 RRFC 040A8h R Receive Undersize CountReceive Fragment Count RUC 040A4h RRJC 040B0h R Receive Oversize CountReceive Jabber Count ROC 040ACh R129. RJC Register Bit Description Management Packets Received Count1Mgtprc 040B4h R Total Octets Received Management Packets Dropped Count1Management Pkts Transmitted Count1 131. Totl and Toth Register Bit Descriptions Total Octets TransmittedTotl 040C8h R/W / Toth 040CCh R 130. Torl and Torh Register Bit DescriptionsTPT 040D4h R Total Packets ReceivedTotal Packets Transmitted TPR 040D0h RPTC127 040DCh R Packets Transmitted 64 Bytes CountPackets Transmitted 65-127 Bytes Count PTC64 040D8h RPTC511 040E4h R Packets Transmitted 128-255 Bytes CountPackets Transmitted 256-511 Bytes Count PTC255 040E0h RPTC1522 040ECh R Packets Transmitted 512-1023 Bytes CountPackets Transmitted 1024 Bytes or Greater Count PTC1023 040E8h RBptc 040F4h R Multicast Packets Transmitted CountBroadcast Packets Transmitted Count Mptc 040F0h RTsctfc 040FCh R TCP Segmentation Context Transmitted CountTCP Segmentation Context Transmit Fail Count Tsctc 040F8h RRdfh 02410h R/W Diagnostics RegistersReceive Data Fifo Head Register Receive Data Fifo Tail RegisterRdfts 02428h R/W Receive Data Fifo Head Saved RegisterReceive Data Fifo Tail Saved Register Rdfhs 02420h R/WTdfh 03410h R/W Receive Data Fifo Packet CountTransmit Data Fifo Head Register Rdfpc 02430h R/WTdfhs 03420h R/W Transmit Data Fifo Tail RegisterTransmit Data Fifo Head Saved Register Tdft 03418h R/WTdfpc 03430h R/W Transmit Data Fifo Tail Saved RegisterTransmit Data Fifo Packet Count Tdfts 03428h R/W152. PBM Bit Description Packet Buffer MemoryPBM 10000h 1FFFCh R/W 151. Tdfpc Register Bit Description370 General Configuration Power Up StateReceive Initialization General Initialization and Reset OperationTransmit Initialization Ipgt IPGR1 IPGR2 Fiber Copper 82544GC/EISignal Ball Name and Function Signal DescriptionsReceive Clock Signal InterfaceCarrier Sense Receive DataMII 10/100 Mbps Differences GMII/MII Features not SupportedSignal Functions Signal Function Pin Gmii 1000 Mbps OperationsDirect PHY Indications to MAC Avoiding Gmii Test Modes MAC ConfigurationSignal Functions Not Supported CTRL.FD Link SetupCTRL.RFCE PHY Initialization 10/100/1000 Mb/s Copper MediaLanpwrgood Reset Operation382 Software Developer’s Manual 383 Initialization of Statistics Loopback DiagnosticsFifo State Fifo DataInternal Loopback TestabilityBypass Instruction Extest InstructionSAMPLE/PRELOAD Instruction Idcode Instruction388 Appendix Changes From 82544EI/82544GC New FeaturesEEC Register ChangesTable A-1. Register Changes Register OffsetSerial Flash Interface 82540EP/EM Differences4 32-Bit PCI Support No TBI/Internal SerDes InterfaceSingle-Port Functionality