Intel Intel Gigabit Ethernet Controllers Transmit Descriptor Base Address High, Tdbah 03804h R/W

Register Descriptions

Field	Bit(s)	Initial	Description
		Value
ZERO	3:0	0b	Zero Value
			This field is ignored on write and reads as 0b.
TDBAL	31:4	X	Transmit Descriptor Base Address Low [31:4]
			This register indicates lower 32 bits of the start address for the
			transmit descriptor ring buffer.

13.4.37Transmit Descriptor Base Address High

TDBAH (03804h; R/W)

This register contains the upper 32 bits of the 64-bit transmit Descriptor base address.

Table 13-80. TDBAH Register Bit Description

31				0
				TDBAH
Field	Bit(s)		Initial	Description
			Value
TDBAH	31:0	X		Transmit Descriptor Base Address [63:32]
				This register indicates upper 32 bits of the start address for the
				transmit descriptor ring buffer.

13.4.38Transmit Descriptor Length

TDLEN (03808h; R/W)

This register determines the number of bytes allocated to the transmit descriptor circular buffer. This value must be a multiple of 128 bytes (the maximum cache line size). Since each descriptor is 16 bits in length, the total number of receive descriptors is always a multiple of eight.

Table 13-81. TDLEN Register Bit Description

31 20 19 7 6 0

Reserved

LEN

0

Field	Bit(s)	Initial	Description
		Value
ZERO	6:0	0b	Ignore on write. Reads back as 0b.

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