General Initialization and Reset Operation

MAC/PHY duplex and speed settings both forced by software (fully-forced link setup) (CTRL.FRCDPLX = 1b, CTRL.FRCSPD = 1b, CTRL.SLU = 1b)

CTRL.FD

Set by software to desired full/half duplex operation (must match

 

duplex setting of PHY)

CTRL.SLU

Must be set to 1b by software to enable communications between MAC

 

and PHY. PHY must also be forced/configured to indicate positive link

 

indication (LINK) to the MAC

CTRL.RFCE

Must be set by S/W to desired flow-control operation (must match flow-

 

control settings of PHY)

CTRL.TFCE

Must be set by S/W to desired flow-control operation (must match flow-

 

control settings of PHY)

CTRL.SPEED

Set by software to desired link speed (must match speed setting of

 

PHY)

STATUS.FD

Reflects the MAC duplex setting written by software to CTRL.FD

STATUS.LU

Reflects 1b (positive link indication LINK from PHY qualified with

 

CTRL.SLU). Note: since both CTRL.SLU and the PHY link indication

 

LINK are forced, this bit set does not GUARANTEE that operation of

 

the link has been truly established.

STATUS.SPEED

Reflects MAC forced speed setting written in CTRL.SPEED

Note: It is important to note that for the Ethernet controller’s link indication (LINK) to be noted by the MAC, the MAC control bit CTRL.SLU must be set to 1b. Normal MAC/PHY speed and duplex configuration are based on observing events on this link indication from the Ethernet controller.

14.6PHY Initialization (10/100/1000 Mb/s Copper Media)

Software needs to determine the PHY address at which the PHY actually resides. This number can be anywhere from 0 to 31.The PHY address is programmable. Board designers can then choose at what PHY address the PHY resides. Software needs to identify the PHY address so that the PHY can be accessed successfully.

To accomplish read and write access to any of the PHY registers, software must program the MDI Control Register (MDIC) with the appropriate data. A PHY is reset at power-up and is enabled to Auto-Negotiate by default. Typically in most environments, by the time the software driver is loaded, the Auto-Negotiation process has completed. However, the PHY might or might not advertise the appropriate capabilities desired by the design. In this instance, it is up to the software to insure that the PHY registers are set up properly to advertise the appropriate Ethernet controller capabilities. For example, by default the Ethernet controller advertises no flow control capabilities in its Auto-Negotiation Advertisement Register (MII Register 4). In order to advertise TX and/or RX Pause capabilities, this register must be modified and Auto-Negotiation re-started to advertise these capabilities to the link partner.

The MII Status Register (PHY Register 1) should be used to check link status.

Software can also force the speed/duplex of a PHY via MII/GMII register access. Note that forcing gigabit speed in a copper environment is not allowed per IEEE specification. Only 10/100 speed and duplex should be forced in the PHY.

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Software Developer’s Manual

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Intel PCI-X, Intel Gigabit Ethernet Controllers manual PHY Initialization 10/100/1000 Mb/s Copper Media, Ctrl.Rfce