Intel Intel Gigabit Ethernet Controllers, PCI-X manual 13.4.25

			Contents
	13.4.25	Receive Descriptor Base Address Low	302
	13.4.26	Receive Descriptor Base Address High	302
	13.4.27	Receive Descriptor Length	303
	13.4.28	Receive Descriptor Head	303
	13.4.29	Receive Descriptor Tail	304
	13.4.30	Receive Delay Timer Register	304
	13.4.31	Receive Interrupt Absolute Delay Timer	305
	13.4.32	Receive Small Packet Detect Interrupt	306
	13.4.33	Transmit Control Register	306
	13.4.34	Transmit IPG Register	308
	13.4.35	Adaptive IFS Throttle - AIT	310
	13.4.36	Transmit Descriptor Base Address Low	311
	13.4.37	Transmit Descriptor Base Address High	312
	13.4.38	Transmit Descriptor Length	312
	13.4.39	Transmit Descriptor Head	313
	13.4.40	Transmit Descriptor Tail	314
	13.4.41	Transmit Interrupt Delay Value	314
	13.4.42	TX DMA Control (82544GC/EI only)	315
	13.4.43	Transmit Descriptor Control	315
	13.4.44	Transmit Absolute Interrupt Delay Value	317
	13.4.45	TCP Segmentation Pad And Minimum Threshold	318
	13.4.46	Receive Descriptor Control	320
	13.4.47	Receive Checksum Control	321
13.5	Filter Registers		323
	13.5.1	Multicast Table Array	323
	13.5.2	Receive Address Low	325
	13.5.3	Receive Address High	325
	13.5.4	VLAN Filter Table Array	326
13.6	Wakeup Registers		327
	13.6.1	Wakeup Control Register	327
	13.6.2	Wakeup Filter Control Register	328
	13.6.3	Wakeup Status Register	329
	13.6.4	IP Address Valid	331
	13.6.5	IPv4 Address Table	332
	13.6.6	IPv6 Address Table	333
	13.6.7	Wakeup Packet Length	334
	13.6.8	Wakeup Packet Memory (128 Bytes)	334
	13.6.9	Flexible Filter Length Table	334
	13.6.10	Flexible Filter Mask Table	335
	13.6.11	Flexible Filter Value Table	336
13.7	Statistics Registers		336
	13.7.1	CRC Error Count	337
	13.7.2	Alignment Error Count	337
	13.7.3	Symbol Error Count	338
	13.7.4	RX Error Count	338
	13.7.5	Missed Packets Count	339
	13.7.6	Single Collision Count	339
	13.7.7	Excessive Collisions Count	340
	13.7.8	Multiple Collision Count	340
	13.7.9	Late Collisions Count	341
Software Developer’s Manual			xi