Intel PCI-X Receive Control Register, Rctl 00100h R/W, Rctl Register Bit Description, Sbp, Upe

Register Descriptions

Field	Bit(s)		Initial	Description
			Value
TXD_LOW	15	X		Clears the mask for Transmit Descriptor Low Threshold hit (not
				applicable to the 82544GC/EI).
SRPD	16	X		Clears mask for Small Receive Packet Detect Interrupt (not
				applicable to the 82544GC/EI).
Reserved	31:17	X		Reserved
				Should be written with 1b to ensure future compatibility.

13.4.22Receive Control Register

RCTL (00100h; R/W)

This register controls all Ethernet controller receiver functions.

Table 13-67. RCTL Register Bit Description

31 27 26 0

Reserved

Receive Control Bits

Field	Bit(s)	Initial	Description
		Value
Reserved	0	0b	Reserved
			Write to 0b for future compatibility.
			Receiver Enable
			The receiver is enabled when this bit is 1b. Writing this bit to 0b
			stops reception after receipt of any in-progress packets. Data
EN	1	0b	remains in the receive FIFO until the device is re–enabled.
			Disabling or re-enabling the receiver does not reinitialize the packet
			filter logic that demarcates packet start and end locations in the
			FIFO; Therefore the receiver must be reset before re-enabling it.
			Store Bad Packets
			0b = do not store.
			1b = store bad packets.
SBP	2	0b	When set, the Ethernet controller stores bad packets (CRC error,
			symbol error, sequence error, length error, alignment error, short
			packets or where carrier extension or RX_ERR errors) that pass the
			filter function in host memory. When the Ethernet controller is in
			promiscuous mode, and SBP is set, it might possibly store all
			packets.
			Unicast Promiscuous Enabled
			0b = Disabled.
UPE	3	0b	1b = Enabled.
			When set, passes without filtering out all received unicast packets.
			Otherwise, the Ethernet controller accepts or rejects unicast
			packets based on the received packet destination address match
			with 1 of the 16 stored addresses.

296 Software Developer’s Manual