Intel PCI-X manual Internal SerDes Interface/TBI Mode- 1Gb/s1, 1.2 8B10B Encoding/Decoding

Ethernet Interface

8.2.1Internal SerDes Interface/TBI Mode– 1Gb/s1

The 82546GB/EB and 82545GM/EM Ethernet controllers contain one or two internal SerDes devices (depending whether or not they support one or two ports). The MAC communicates with the SerDes over a TBI interface. Normally, this interface is not exposed externally.

For the 82554GC/EI, TBI mode is selectable via an external pin TBI-MODE. Software cannot override this pin. This interface has 125 Mb/s 10-bit data paths for both receive and transmit. The clock at the transmit interface operates at 125 MHz; the receive interface has two clocks running at

62.5MHz that are 180 degrees out of phase as follows:

• RX_DATA: 10-bit receive data bus

• TX_DATA: 10-bit transmit data bus

•RBC0/I_RBC1: Receive clocks (62.5 MHz; 180 degree phase shift between I_RBC0 and I_RBCI)

•GTX_CLK: Transmit clock (125 MHz)

8.2.1.1Gigabit Physical Coding Sub-Layer (PCS) for the Internal SerDes2

The Ethernet controller integrates the 802.3z PCS function on-chip. The on-chip PCS circuitry is used when the link interface is configured for internal SerDes mode and is bypassed in internal PHY mode.

The packet encapsulation is based on the Fibre Channel physical layer (FC0/FC1) and uses the same coding scheme to maintain transition density and DC balance. The physical layer device is a SerDes and is used for 1000BASE-SX, -LX, or -CX configurations.

8.2.1.28B10B Encoding/Decoding

The Gigabit PCS circuitry uses the same transmission coding scheme used in the Fibre Channel physical layer specification. The 8B10B coding scheme was chosen by the IEEE standards committee in order to provide a balanced, continuous stream with sufficient transition density to allow for clock recovery at the receiving station. There is a 25 percent overhead for this transmission code which accounts for the data signaling rate of 1250 Mb/s with 1000 Mb/s of actual data.

1.TBI (10-Bit Interface) - 1GB/s for the 82554GC/EI.

2.Gigabit Physical Coding Sub-Layer (PCS) for TBI (82554GC/EI).

154 Software Developer’s Manual