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Intel PCI, PCI-X, Intel Gigabit Ethernet Controllers manual 244

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Register Descriptions

13.4.7.1.2 PHY Status Register

PSTATUS (01d; R)

Table 13-17. PHY Status Register Bit Description

Field Bit(s) Description Mode HW Rst SW Rst

Extended Capability 01b = Extended register capabilities. RO Always 1b

Jabber Detect 11b = Jabber condition detected.

0b = Jabber condition not detected.

RO,L

H0b 0b

Link Status 2

1b = Link is up.

0b = Link is down.

This register indicates whether link was

lost after the last read. For the current

link status, either read this register

back-to-back or read the Link Real Time

bit 17 in the PHY Specific Status

Register.

RO,

LL 0b 0b

Auto-Negotiation

Ability 31b = PHY able to perform Auto-

Negotiation. RO Always 1b

Remote Fault 4

1b = Remote fault condition detected.

0b = Remote fault condition not

detected.

RO,L

H0b 0b

Auto-Negotiation

Complete 5

1b = Auto-Negotiation process

complete.

0b = Auto-Negotiation process not

complete.

RO 0b 0b

MF Preamble

Suppression 61b = PHY accepts management frames

with preamble suppressed. RO

Always 1b

(0b for the 82541xx

and 82547GI/EI)

Reserved 7Reserved. Should be set to 0b RO Always 0b

Extended Status 81b = Extended status information in the

Extended PHY Status Register (15d). RO Always 1b

100BASE-T2 Half

Duplex 90b = PHY not able to perform half

duplex 100BASE-T2. RO Always 0b

100BASE-T2 Full

Duplex 10 0b = PHY not able to perform full duplex

100BASE-T2. RO Always 0b

10 Mb/s Half Duplex 11

1b = PHY able to perform half duplex

10BASE-T.

0b = PHY not able to perform half

duplex 10BASE-T.

82544GC/EI only:

Bit 14 = Bit 13 = Bit 12 = Bit 11 =

(MODE[3:0] is not any of xx01b, 1x00b,

001xb, 0111b).

RO

RO

1b

MODE[3:0]

Contents

Main ii Software Developers Manual Software Developers Manual iii Revision History Page Contents 1 Introduction 2 Architectural Overview 3 Receive and Transmit Description 4 PCI Local Bus Interface 5 EEPROM Interface 7 FLASH Memory Interface 6 Power Management 8 Ethernet Interface 9 802.1q VLAN Support 10 Configurable LED Outputs 11 PHY Functionality and Features 12 Dual Port Characteristics 13 Register Descriptions Page Page 14 General Initialization and Reset Operation 15 Diagnostics and Testability A Appendix (Changes From 82544EI/82544GC) B Appendix (82540EP/EM and 82545GM/EM Differences) Page Introduction 1 1.1 Scope 1.2 Overview 1.3 Ethernet Controller Features Page Page Page 1.4 Conventions 1.5 Related Documents 1.6 Memory Alignment Terminology Architectural Overview 2 2.1 Introduction 8Software Developers Manual Architectural Overview Figure 2-2. 82545GM/EM, 82544GC/EI, 82540EP/EM, and 82541xx External Interface 2.2 External Architecture Figure 2-1 shows the external interfaces to the 82546GB/EB. Device Function 0 MAC/Controller (LAN A) Device Function 1 MAC/Controller (LAN B) 10/100/1000 PHY Software Developers Manual 9 Architectural Overview Figure 2-3 shows the external interfaces to the 82547GI/EI. Figure 2-3. 82547GI(EI) External Interface 2.3 Microarchitecture 2.3.1 PCI/PCI-X Core Interface 2.3.2 82547GI/EI CSA Interface 2.3.3 DMA Engine and Data FIFO 2.3.4 10/100/1000 Mb/s Receive and Transmit MAC Blocks 2.3.5 MII/GMII/TBI/Internal SerDes Interface Block 2.3.6 10/100/1000 Ethernet Transceiver (PHY) 2.3.7 EEPROM Interface 2.3.8 FLASH Memory Interface 2.4 DMA Addressing 2.5 Ethernet Addressing 2.6 Interrupts 2.7 Hardware Acceleration Capability 2.7.1 Checksum Offloading 2.7.2 TCP Segmentation 2.8 Buffer and Descriptor Structure Page Receive and Transmit Description 3 3.1 Introduction 3.2 Packet Reception 3.2.1 Packet Address Filtering 3.2.2 Receive Data Storage 3.2.3 Receive Descriptor Format 256 B 512 B 1024 B 3.2.3.1 Receive Descriptor Status Field 22 Software Developers Manual 3.2.3.2 Receive Descriptor Errors Field Software Developers Manual 23 Table 3-3. Receive Errors (RDESC.ERRORS) Layout 3.2.3.3 Receive Descriptor Special Field 3.2.4 Receive Descriptor Fetching 3.2.5 Receive Descriptor Write-Back 3.2.5.1 Receive Descriptor Packing 3.2.5.2 Null Descriptor Padding Page 3.2.7 Receive Interrupts 3.2.7.1 Receive Timer Interrupt 3.2.7.1.1 Receive Interrupt Delay Timer / Packet Timer (RDTR) 3.2.7.1.2 Receive Interrupt Absolute Delay Timer (RADV) 3.2.7.2 Small Receive Packet Detect 3.2.7.3 Receive Descriptor Minimum Threshold (ICR.RXDMT) 3.2.7.4 Receiver FIFO Overrun 3.2.8 82544GC/EI Receive Interrupts 3.2.9 Receive Packet Checksum Offloading 3.2.9.1 MAC Address Filter 3.2.9.2 SNAP/VLAN Filter 3.2.9.3 IPv4 Filter 3.2.9.4 IPv6 Filter 3.2.9.5 UDP/TCP Filter 3.3 Packet Transmission 3.3.1 Transmit Data Storage 3.3.2 Transmit Descriptors 3.3.3 Legacy Transmit Descriptor Format Page 38 Software Developers Manual 3.3.3.1 Transmit Descriptor Command Field Format 3.3.3.2 Transmit Descriptor Status Field Format 3.3.4 Transmit Descriptor Special Field Format 3.3.5 TCP/IP Context Transmit Descriptor Format 3.3.6 TCP/IP Context Descriptor Layout Software Developers Manual 43 Table 3-14. Transmit Descriptor (TDESC) Layout 3.3.6.1 TCP/UDP Offload Transmit Descriptor Command Field Page 3.3.6.2 TCP/UDP Offload Transmit Descriptor Status Field 3.3.7 TCP/IP Data Descriptor Format Software Developers Manual 47 Table 3-17. Transmit Descriptor (TDESC) Layout (Type = 0001b) 48 Software Developers Manual 3.3.7.1 TCP/IP Data Descriptor Command Field 3.3.7.2 TCP/IP Data Descriptor Status Field 50 Software Developers Manual 3.3.7.3 TCP/IP Data Descriptor Option Field The SPECIAL field is used to provide the 802.1q/802.3ac tagging information. 3.3.7.4 TCP/IP Data Descriptor Special Field 3.4 Transmit Descriptor Ring Structure Page 3.4.1 Transmit Descriptor Fetching 3.4.2 Transmit Descriptor Write-back 3.4.3 Transmit Interrupts 3.4.3.1 Delayed Transmit Interrupts 3.5 TCP Segmentation Page Page 3.5.5 TCP Segmentation Indication 3.5.6 TCP Segmentation Use of Multiple Data Descriptors 3.5.7 IP and TCP/UDP Headers Page Page 3.5.8 Transmit Checksum Offloading with TCP Segmentation 3.5.9 IP/TCP/UDP Header Updating 66 Software Developers Manual Figure 3-19. Overall Data Flow TCP Segmentation Data Flow Events Scheduling 3.5.9.1 TCP/IP/UDP Header for the First Frame 3.6 IP/TCP/UDP Transmit Checksum Offloading Page Page PCI Local Bus Interface 4 4.1 PCI Configuration Page Page 74 Software Developers Manual All base address registers have the following fields: Page Page Page 78 Software Developers Manual Table 4-4. Status Register Layout 4.1.1 PCI-X Configuration Registers 4.1.1.1 PCI-X Capability ID 4.1.1.2 Next Capability 80 Software Developers Manual 4.1.1.3 PCI-X Command Software Developers Manual 81 4.1.1.4 PCI-X Status 82 Software Developers Manual 4.1.2 Reserved and Undefined Addresses 4.1.3 Message Signaled Interrupts 4.1.3.1 Message Signaled Interrupt Configuration Registers 4.1.3.1.1 MSI Capability ID 4.1.3.1.2 Next Capability 84 Software Developers Manual 4.1.3.1.3 Message Control Software Developers Manual 85 4.1.3.1.4 Message Address 4.1.3.1.5 Message Upper Address 4.1.3.1.6 Message Data 4.2 Commands Table 4-5. PCI and PCI-X Encoding Difference Page 4.3 PCI/PCI-X Command Usage 4.3.1 Memory Write Operations 4.3.1.1 MWI Bursts 4.3.1.2 MW Bursts 4.3.2 Memory Read Operations 4.3.2.1 PCI-X Command Usage 4.4 Cache Line Information 4.4.1 Target Transaction Termination 4.5 Interrupt Assignment (82547GI/EI Only) 4.6 LAN Disable 4.7 CardBus Application (82541PI/GI/EI Only) EEPROM Interface 5 5.1 General Overview 94 Software Developers Manual 5.2 Component Identification Via Programming Interface 5.3 EEPROM Device and Interface 5.3.1 Software Access 5.4 Signature and CRC Fields 5.5 EEUPDATE Utility 5.5.1 Command Line Parameters 98 Software Developers Manual 5.6 EEPROM Address Map Software Developers Manual 99 100 Software Developers Manual Software Developers Manual 101 102 Software Developers Manual Table 5-3. 82544GC/EI and 82541ER EEPROM Address Map 5.6.1 Ethernet Address (Words 00h-02h) 5.6.2 Software Compatibility Word (Word 03h) 5.6.3 SerDes Configuration (Word 04h) 5.6.4 EEPROM Image Version (Word 05h) 5.6.5 Compatibility Fields (Word 05h - 07h) 5.6.6 PBA Number (Word 08h, 09h) Software Developers Manual 105 5.6.7 Initialization Control Word 1 (Word 0Ah) The first word read by the Ethernet controller contains initialization values that: Table 5-5. Initialization Control Word 1 (Word 0Ah) 106 Software Developers Manual Table 5-5. Initialization Control Word 1 (Word 0Ah) 5.6.8 Subsystem ID (Word 0Bh) 5.6.9 Subsystem Vendor ID (Word 0Ch) 5.6.10 Device ID (Word 0Dh, 11h1) 5.6.11 Vendor ID (Word 0Eh) 5.6.12 Initialization Control Word 2 (Word 0Fh) 108 Software Developers Manual Table 5-6. Initialization Control Word 2 (Word 0Fh) 5.6.13 PHY Register Address Data (Words 10h, 11h, and 13h - 1Eh) 5.6.14 OEM Reserved Words (Words 10h, 11h, 13h - 1Fh) 5.6.15 EEPROM Size (Word 12h) 5.6.16 Common Power (Word 12h) 5.6.17 Software Defined Pins Control (Word 10h1, 20h) 110 Software Developers Manual Table 5-8. Software Defined Pins Control (Word 10h, 20h) 5.6.18 CSA Port Configuration 2 (Word 21h) Page Software Developers Manual 113 5.6.24 Management Control (Word 13h1, 23h2) Table 5-10. Initial Management Control Register Settings 5.6.25 SMBus Slave Address (Word 14h Software Developers Manual 115 5.6.26 Initialization Control 3 (Word 14h This word controls the general initialization values. Table 5-12. Initialization Control 3 5.6.27 IPv4 Address (Words 15h - 16h1 and 25h - 26h) 5.6.28 IPv6 Address (words 17h - 1Eh1 and 27h - 2Eh) 5.6.29 LED Configuration Defaults (Word 2Fh)2 5.6.30 Boot Agent Main Setup Options (Word 30h) Software Developers Manual 117 Table 5-15. Boot Agent Main Setup Options 5.6.31 Boot Agent Configuration Customization Options (Word 31h) Software Developers Manual 119 . Table 5-16. Boot Agent Configuration Customization Options (Word 31h) 5.6.32 Boot Agent Configuration Customization Options (Word 32h) 5.6.33 IBA Capabilities (Word 33h) 5.6.34 IBA Secondary Port Configuration (Words 34h-35h) 5.6.35 Checksum Word Calculation (Word 3Fh) 5.6.36 82546GB/EB Dual-Channel Fiber Wake on LAN (WOL) Mode and Functionality (Word 0Ah, 20h) 5.6.37 EEPROM Images 5.7 Parallel FLASH Memory Page FLASH Memory Interface 7 7.1 FLASH Interface Operation 7.2 FLASH Control and Accesses 7.2.1 Read Accesses 7.2.2 Write Accesses Page Page Power Management 6 6.1 Introduction to Power Management 6.2 Assumptions 6.3 D3cold support 6.3.1 Power States 6.3.1.1 Dr State 6.3.1.2 D0u State 6.3.1.3 D0a (D0 active) 6.3.1.4 D3 6.3.2 Timing Software Developers Manual 133 6.3.2.1 Power Up (Off to Dr to D0u to D0a) Figure 6-2. Startup Timing 134 6.3.2.2 Transition From D0a to D3 and Back Without PCI Reset Figure 6-3. Transition from D0a to D3 and Back Without PCI Reset Software Developers Manual 135 6.3.2.3 Transition From D0a to D3 and Back with PCI Reset Figure 6-4. Transition From D0a to D3 and Back with PCI Reset 136 6.3.2.4 PCI Reset Without Transition to D3 Figure 6-5. PCI Reset Sequence 6.3.3 PCI Power Management Registers 6.3.3.1 Capability ID 1 Byte Offset = 0 (RO) 6.3.3.2 Next Item Pointer 1 Byte Offset = 1 (RO) 138 6.3.3.3 Power Management Capabilities - (PMC) 2 Bytes Offset = 2 (RO) Software Developers Manual 139 6.3.3.4 Power Management Control / Status Register - (PMCSR) 2 Bytes Offset = 4 (RO) PME_En and PME_Status. 6.3.3.5 PMCSR_BSE Bridge Support Extensions 6.3.3.6 Data Register 6.4 Wakeup 6.4.1 Advanced Power Management Wakeup 6.4.2 ACPI Power Management Wakeup 6.4.3 Wakeup Packets 6.4.3.1 Pre-Defined Filters 6.4.3.1.3 Broadcast Page 146 6.4.3.1.5 ARP/IPv4 Request Packet Software Developers Manual 147 6.4.3.1.6 Directed IPv4 Packet 148 6.4.3.2 Directed IPv6 Packet 6.4.3.3 Flexible Filter 6.4.3.3.1 IPX Diagnostic Responder Request Packet Example 150 6.4.3.3.2 Directed IPX Packet Example 82541xx and 82547GI/EI Only 6.4.3.4 IPv6 Neighbor Discovery Filter Software Developers Manual 151 6.4.3.5 Wakeup Packet Storage Page Ethernet Interface 8 8.1 Introduction 8.2 Link Interfaces Overview 8.2.1 Internal SerDes Interface/TBI Mode 1Gb/s 8.2.1.1 Gigabit Physical Coding Sub-Layer (PCS) for the Internal SerDes2 8.2.1.2 8B10B Encoding/Decoding 8.2.1.3 Code Groups and Ordered Sets 8.2.2 GMII 1 Gb/s 8.2.3 MII 10/100 Mb/s 8.3 Internal Interface 8.4 Duplex Operation 8.4.1 Full Duplex 8.4.2 Half Duplex 8.4.2.1 Carrier Extension (1000 Mb/s Only) 8.4.2.2 Packet Bursting 8.5 Auto-Negotiation and Link Setup 8.6 Auto-Negotiation and Link Setup 8.6.1 Link Configuration in Internal Serdes/TBI Mode1 8.6.1.1 Link Speed 8.6.1.2 Auto-Negotiation 8.6.1.3 Hardware Auto-Negotiation 8.6.1.4 Software Auto-Negotiation 8.6.1.5 Forcing Link 8.6.2 Internal GMII/MII Mode 8.6.2.1 Auto-Negotiation 8.6.2.2 Link Speed Page 166 Ethernet Interface 8.6.3 Internal SerDes Mode1 Control Bit Resolution Table 8-3. Internal Serdes Mode1 Hardware Enabled TXCW.ANE = 1b Table 8-4. Internal Serdes1 Mode Software Enabled TXCW.ANE = 0b 8.6.4 Internal PHY Mode Control Bit Resolution 168 Ethernet Interface Table 8-7. GMII/MII Mode Auto-Speed Detection CTRL.FRCSPD = 1b; CTRL.FRCDPLX = 0b; CTRL.ASDE = X CTRL.FRCSPD = CTRL.FRCDPLX = 0b; CTRL.ASDE = 1b Table 8-8. GMII/MII Mode Force Speed 8.6.5 Loss of Signal/Link Status Indication 8.6.5.1 Internal Serdes Mode 8.6.5.2 Internal PHY Mode 8.7 10/100 Mb/s Specific Performance Enhancements 8.7.1 Adaptive IFS 8.7.2 Flow Control 8.7.3 MAC Control Frames & Reception of Flow Control Packets Page 8.7.4 Discard PAUSE Frames and Pass MAC Control Frames 8.7.5 Transmission of PAUSE Frames 8.7.6 Software Initiated PAUSE Frame Transmission 8.7.7 External Control of Flow Control Operation 802.1q VLAN Support 9 9.1 802.1q VLAN Packet Format 9.1.1 802.1q Tagged Frames 9.2 Transmitting and Receiving 802.1q Packets 9.2.1 Adding 802.1q Tags on Transmits 9.2.2 Stripping 802.1q Tags on Receives 9.3 802.1q VLAN Packet Filtering Page Page Configurable LED Outputs 10 10.1 Configurable LED Output s 10.1.1 Selecting an LED Output Source 10.1.2 Polarity Inversion 10.1.3 Blink Control Page Page PHY Functionality and Features 11 11.1 Auto-Negotiation 11.1.1 Overview 11.1.2 Next Page Exchanges 11.1.3 Register Update 11.1.4 Status 11.2 MDI/MDI-X Crossover (copper only) 11.2.1 Polarity Correction (copper only) 11.2.2 10/100 Downshift (82540EP/EM Only) 11.3 Cable Length Detection (copper only) 11.4 PHY Power Management (copper only) 11.4.1 Link Down Energy Detect (copper only) 11.4.2 D3 State, No Link Required (copper only) 11.4.3 D3 Link-Up, Speed-Management Enabled (copper only) 11.4.4 D3 Link-Up, Speed-Management Disabled (copper only) 11.5 Initialization 11.5.1 MDIO Control Mode 11.6 Determining Link State 11.6.1 False Link 11.6.2 Forced Operation 11.6.3 Auto Negotiation 11.6.4 Parallel Detection 11.7 Link Criteria 11.7.1 1000BASE-T 11.7.2 100BASE-TX 11.7.3 10BASE-T 11.8 Link Enhancements 11.8.1 SmartSpeed 11.8.1.1 Using SmartSpeed 11.8.2 Flow Control 11.9 Management Data Interface 11.10 Low Power Operation 11.10.1 Powerdown via the PHY Register 11.10.2 Smart Power-Down 11.11 1000 Mbps Operation 11.11.1 Introduction Page 11.11.2 Transmit Functions 11.11.2.1 Scrambler 11.11.3 Transmit FIFO 11.11.3.1 Transmit Phase-Locked Loop PLL 11.11.3.2 Trellis Encoder 11.11.3.4 Spectral Shaper 11.11.3.5 Low-Pass Filter 11.11.3.6 Line Driver 11.11.3.7 Transmit/Receive Flow 11.11.4 Receive Functions 11.11.4.6 Descrambler 11.11.4.7 Viterbi Decoder/Decision Feedback Equalizer (DFE) 11.11.4.8 4DPAM5 Decoder 11.12 100 Mbps Operation 11.13 10 Mbps Operation 11.13.1 Link Test 11.13.2 10Base-T Link Failure Criteria and Override 11.13.3 Jabber 11.14 PHY Line Length Indication Page Dual Port Characteristics 12 12.1 Introduction 12.2 Features of Each MAC 12.2.1 PCI/PCI-X interface 204 Dual Port Characteristics 12.2.2 MAC Configuration Register Space 12.2.3 SDP, LED, INT# output 12.3 Shared EEPROM 12.3.1 EEPROM Map 12.3.2 EEPROM Arbitration 12.4 Shared FLASH 12.4.1 FLASH Access Contention 12.5 LAN Disable 12.5.1 Overview 12.5.2 Values Sampled on Reset 12.5.3 Multi-Function Advertisement 12.5.4 Interrupt Use 12.5.5 Power Reporting 210 Dual Port Characteristics 12.5.6 Summary The following table lists the various LAN enabled/disabled configurations possible: Register Descriptions 13 13.1 Introduction 13.2 Register Conventions 13.2.1 Memory and I/O Address Decoding 13.2.1.1 Memory-Mapped Access to Internal Registers and Memories 13.2.1.2 Memory-Mapped Access to FLASH 13.2.1.3 Memory-Mapped Access to Expansion ROM 13.2.2 I/O-Mapped Internal Register, Internal Memory, and Flash1 13.2.2.1 IOADDR 13.2.2.2 IODATA Page Software Developers Manual 215 Table 13-2. Ethernet Controller Register Summary 216 Software Developers Manual 217 218 13.3 PCI-X Register Access Split 13.4 Main Register Descriptions 13.4.1 Device Control Register CTRL (00000h; R/W) Software Developers Manual 221 Table 13-3. CTRL Register Bit Description 222 Software Developers Manual 223 224 13.4.2 Device Status Register STATUS (00008h; R) 226 Table 13-5. Status Register Bit Description Software Developers Manual 227 228 13.4.3 EEPROM/Flash Control & Data Register EECD (00010h; R/W) Table 13-6. EECD Register Bit Description 82544GC/EI Only Software Developers Manual 229 Note: Attempts to write to the FLASH device when writes are disabled (FEW = 01b) should not be 230 13.4.4 EEPROM Read Register EERD (00014h; RW) Table 13-7. EEPROM Read Register Bit Description Page 232 13.4.5 Flash Access FLA (0001Ch; R/W) Table 13-9. Flash Access FLA Software Developers Manual 233 13.4.6 Extended Device Control Register CTRL_EXT (00018h, R/W) 234 Software Developers Manual 235 Table 13-11. GPI to SDP Bit Mappings 236 Table 13-12. 82544GC/EI CTRL_EXT Register Bit Description Software Developers Manual 237 Table 13-13. 82544GC/EI GPI to SDP Bit Mapping 13.4.7 MDI Control Register Software Developers Manual 239 Table 13-14. MDI Control Register Bit Description 13.4.7.1 PHY Registers Software Developers Manual 241 13.4.7.1.1 PHY Control Register PCTRL (00d; R/W) 242 Software Developers Manual 243 244 13.4.7.1.2 PHY Status Register PSTATUS (01d; R) Table 13-17. PHY Status Register Bit Description Software Developers Manual 245 Table 13-17. PHY Status Register Bit Description 246 13.4.7.1.3 PHY Identifier Register (LSB) PID (02d; R) 13.4.7.1.4 Extended PHY Identifier Register (MSB) EPID (03d; R) Table 13-18. PHY Identifier Bit Description Table 13-19. Extended PHY Identifier Bit Description Software Developers Manual 247 248 Software Developers Manual 249 Table 13-20. Auto-Negotiation Advertisement Register Bit Description 250 82544GC/EI Only: Page 252 82544GC/EI Only: Table 13-23. Link Partner Ability Register (Base Page) Bit Description Software Developers Manual 253 82541xx and 82547GI/EI Only: T able 13-24. PHY Link Page Ability Bit Description 254 13.4.7.1.7 Auto-Negotiation Expansion Register ANE (06d; R) Table 13-25. Auto-Negotiation Expansion Register Bit Description Software Developers Manual 255 256 Software Developers Manual 257 258 13.4.7.1.11 1000BASE-T Status Register GSTATUS (10d; R) Table 13-28. 1000BASE-T Control Register Bit Description Table 14-29. 1000BASE-T Status Register Bit Description Software Developers Manual 259 13.4.7.1.12 Extended PHY Status Register EPSTATUS (15d; R) Table 14-29. 1000BASE-T Status Register Bit Description Table 13-30. Extended PHY Status Register Bit Description 260 Software Developers Manual 261 PHY Port Configuration Register (82541xx and 82547GI/EI Only) PPCONF (16d; R/W) Table 13-32. PHY Port Configuration Register Bit Description Table 13-31. PHY Specific Control Register Bit Description 262 Table 13-32. PHY Port Configuration Register Bit Description Software Developers Manual 263 264 Table 13-33. PHY Specific Status Register Bit Description Software Developers Manual 265 266 13.4.7.1.15 PHY Interrupt Enable Register PINTE (18d; R/W) Table 13-34. PHY Status 1 Register Bit Description Table 13-35. PHY Interrupt Enable Bit Description Software Developers Manual 267 PHY Port Control Register (82541xx and 82547GI/EI Only) PPCONT (18d; R/W) Table 13-36. PHY Port Control Register Bit Description Table 13-35. PHY Interrupt Enable Bit Description 268 13.4.7.1.16 PHY Interrupt Status Register PINTS (19d; R) Table 13-36. PHY Port Control Register Bit Description Table 13-37. PHY Interrupt Status Bit Description Software Developers Manual 269 PHY Link Health Register (82541xx and 82547GI/EI Only) PLINK (19d; R) Table 13-38. PHY Link Health Register Bit Description Table 13-37. PHY Interrupt Status Bit Description 270 Table 13-38. PHY Link Health Register Bit Description Software Developers Manual 271 13.4.7.1.17 Extended PHY S pecific Contro l Register 1 EPSCON1 (20d; R/W) T able 13-39. Extended PHY Specific Control 1 Bit Description 272 GMII FIFO Register (82541xx and 82547GI/EI Only) PFIFO (20d; R/W) Table 13-40. GMII FIFO Register Bit Description Page 274 Table 13-43. SPEED_TEN_LED and LINK_ACT_LED Bit Description Software Developers Manual 275 13.4.7.1.20 PHY Global Status (82544GC/EI Only) PGSTAT (23d; R) 13.4.7.1.21 SPEED_100_LED and SPEED_1000_LED Control (82541xx and 82547GI/EI Only) (24d; R/W) Table 13-44. PHY Global Status Bit Description Table 13-45. SPEED_100_LED and SPEED_1000_LED Bit Description 276 13.4.7.1.22 PHY LED Control Register (82544GC/EI Only) PLED (24d; R/W) Table 13-45. SPEED_100_LED and SPEED_1000_LED Bit Description Table 13-46. PHY LED Control Bit Description Page 278 13.4.7.1.26 MDI Register 30 Access Window R30AW (30d; R/W) 13.4.7.1.27 Documented MDI Register 30 Operations1 Table 13-50. MDI Register 30 Page Select Bit Description Table 13-51. MDI Register 30 Operations 13.4.8 Flow Control Address Low FCAL (00028h; R/W) 13.4.9 Flow Control Address High FCAH (0002Ch; R/W) 13.4.10 Flow Control Type FCT (00030h; R/W) 13.4.11 VLAN Ether Type VET (00038h; R/W) Software Developers Manual 281 13.4.12 Flow Control Transmit Timer Value FCTTV (00170h; R/W) 282 13.4.13 T ransmit Configuration W ord Regi ster TXCW (00178h; R/W) Table 13-58. TXCW Register Bit Description 13.4.14 Receive Configuration Word Register1 RXCW (00180h; R) 284 Table 13-59. RXCW Register Bit Description Software Developers Manual 285 13.4.15 LED Control LEDCTL (00E00h; RW) 286 T able 13-60. LED Contr ol Bit Description 13.4.15.1 MODE Encodings for LED Output s Note: All 16 modes listed are functional. Software Developers Manual 287 T able 13-61. Mode Encoding s for LED Output s 288 13.4.16 Packet Buffer Allocation Table 13-62. PBA Register Bit Description PBA (01000H; R/W) Software Developers Manual 289 13.4.17 Interrupt Cause Read Register ICR (000C0H; R) Table 13-63. ICR Register Bit Description 290 13.4.18 Interrupt Throttling Regi ster ITR (000C4h; R/W) 292 13.4.19 Interrupt Cause Set Register ICS (000C8h; W) Table 13-64. ICS Register Bit Description 13.4.20 Interrupt Mask Set/Read Register IMS (000D0h; R/W) 13.4.21 Interrupt Mask Clear Register IMC (000D8h; W) Page 296 13.4.22 Receive Control Register Table 13-67. RCTL Register Bit Description RCTL (00100h; R/W) This register controls all Ethernet controller receiver functions. Software Developers Manual 297 298 Software Developers Manual 299 13.4.23 Flow Control Receive Threshold Low FCRTL (02160h; R/W) Software Developers Manual 301 13.4.24 Flow Control Receive Threshold High FCRTH (02168h; R/W) Table 13-69. FCRTH Register Bit Description 13.4.25 Receive Descriptor Base Address Low RDBAL (02800h;R/W) 13.4.26 Receive Descriptor Base Address High RDBAH (02804h; R/W) 13.4.27 Receive Descriptor Length RDLEN (02808h; R/W) 13.4.28 Receive Descriptor Head RDH (02810h; R/W) 13.4.29 Receive Descriptor Tail RDT (02818h;R/W) 13.4.30 Receive Delay Timer Register RDTR (02820h; R/W) 13.4.31 Receive Interrupt Absolute Delay Timer1 RADV (0282Ch; RW) 13.4.32 Receive Small Packet Detect Interrupt1 RSRPD (02C00h; R/W) 13.4.33 Transmit Control Register TCTL (00400h;R/W) Software Developers Manual 307 Table 13-76. TCTL Register Bit Description 308 This register controls the IPG (Inter Packet Gap) timer for the Ethernet controller. Figure 13-1. Carrier Extended Frame Format (82541xx and 82547GI/EI) 13.4.34 Transmit IPG Register TIPG (00410;R/W) Software Developers Manual 309 Table 13-77. TIPG Register Bit Description 13.4.35 Adaptive IFS Throttle - AIT AIFS (00458;R/W) Software Developers Manual 311 Table 13-78. AIFS Register Bit Description Table 13-79. TDBAL Register Bit Description 13.4.36 Transmit Descriptor Base Address Low TDBAL (03800h; R/W) 312 13.4.37 Transmit Descriptor Base Address High Table 13-81. TDLEN Register Bit Description TDBAH (03804h; R/W) This register contains the upper 32 bits of the 64-bit transmit Descriptor base address. Table 13-80. TDBAH Register Bit Description 13.4.39 Transmit Descriptor Head TDH (03810h; R/W) 13.4.40 Transmit Descriptor Tail TDT (03818h; R/W) 13.4.41 Transmit Interrupt Delay Value TIDV (03820h; R/W) Software Developers Manual 315 13.4.42 TX DMA Control (82544GC/EI only) TXDMAC (03000h; R/W) This register controls the transmit DMA pre-fetching and preemption abilities. Table 11-85. TXDMAC Register Bit Description 13.4.43 Transmit Descriptor Control 316 Table 13-86. TXDCTL Register Bit Description 13.4.44 Transmit Absolute Interrupt Delay Value1 TADV (0382Ch; RW) 13.4.45 TCP Segmentation Pad And Minimum Threshold TSPMT (03830h; RW) Page 320 13.4.46 Receive Descriptor Control RXDCTL (02828h; R/W) Table 13-87. RXDCTL Register Bit Description Software Developers Manual 321 13.4.47 Receive Checksum Control Table 13-88. RXCSUM Register Bit Description RXCSUM (05000h; R/W) 322 13.5 Filter Registers 13.5.1 Multicast Table Array MTA[127:0] (05200h-053FCh; R/W) 47:40 39:32 31:24 23:16 15:8 7:0 bank[1:0] Destination Addres s Multicast Table Array 32 x 128 (4096-bit vector) ... ... 13.5.2 Receive Address Low RAL (05400h + 8*n; R/W) 13.5.3 Receive Address High RAH (05404h + 8n; R/W) 13.5.4 VLAN Filter T able Array VFTA[127:0] (05600h 057FCh; R/W) Software Developers Manual 327 Table 13-92. VFTA[127:0] Bit Description 13.6 Wakeup Registers 13.6.1 Wakeup Control Register WUC (05800h; R/W) 328 13.6.2 Wakeup Filter Control Register WUFC (05808h; R/W) Software Developers Manual 329 13.6.3 Wakeup Status Register WUS (05810h; R) 330 Software Developers Manual 331 13.6.4 IP Address Valid IPAV (5838h; R/W) 332 13.6.5 IPv4 Address T able IP4A T (05840h - 05858h; R/W) Note: This table is not cleared by any reset. Software Developers Manual 333 13.6.6 IPv6 Address T able IP6AT (05880h - 0588Ch; R/W) Note: This table is not cleared by any reset. 13.6.7 Wakeup Packet Length WUPL (05900h; R/W) 13.6.8 Wakeup Packet Memory (128 Bytes) WUPM (05A00h - 05A7Ch; R/W) 13.6.9 Flexible Filter Length Table 13.6.10 Flexible Filter Mask Table FFMT (09000h - 093F8h; R/W) 13.6.11 Flexible Filter Value Table FFVT (09800h - 09BF8h; R/W) 13.7 Statistics Registers 13.7.1 CRC Error Count CRCERRS (04000h; R) 13.7.2 Alignment Error Count ALGNERRC (04004h; R) 13.7.3 Symbol Error Count SYMERRS (04008h; R) 13.7.4 RX Error Count RXERRC (0400Ch; R) 13.7.5 Missed Packets Count MPC (04010h; R) 13.7.6 Single Collision Count SCC (04014h; R) 13.7.7 Excessive Collisions Count ECOL (04018h; R) 13.7.8 Multiple Collision Count MCC (0401Ch; R) 13.7.9 Late Collisions Count LATECOL (04020h; R) 13.7.10 Collision Count COLC (04028h; R) 13.7.11 Defer Count DC (04030h; R) 13.7.12 Transmit with No CRS TNCRS (04034h; R) 13.7.13 Sequence Error Count SEC (04038h; R) 13.7.14 Carrier Extension Error Count CEXTERR (0403Ch; R) 13.7.15 Receive Length Error Count RLEC (04040h; R) 13.7.16 XON Received Count XONRXC (04048h; R) 13.7.17 XON Transmitted Count XONTXC (0404Ch; R) 13.7.18 XOFF Received Count XOFFRXC (04050h; R) 13.7.19 XOFF Transmitted Count 13.7.20 FC Received Unsupported Count FCRUC (04058h; R) 13.7.21 Packets Received (64 Bytes) Count PRC64 (0405Ch; R) 13.7.22 Packets Received (65-127 Bytes) Count PRC127 (04060h; R) 13.7.23 Packets Received (128-255 Bytes) Count PRC255 (04064h; R) 13.7.24 Packets Received (256-511 Bytes) Count PRC511 (04068h; R) 13.7.25 Packets Received (512-1023 Bytes) Count PRC1023 (0406Ch; R) 13.7.26 Packets Received (1024 to Max Bytes) Count PRC1522 (04070h; R) 13.7.27 Good Packets Received Count GPRC (04074h; R) 13.7.28 Broadcast Packets Received Count BPRC (04078h; R) 13.7.29 Multicast Packets Received Count MPRC (0407Ch; R) 13.7.30 Good Packets Transmitted Count GPTC (04080h; R) 13.7.31 Good Octets Received Count GORCL (04088h; R)/GORCH (0408Ch; R) 13.7.32 Good Octets Transmitted Count GOTCL (04090h; R)/ GOTCH (04094; R) 13.7.33 Receive No Buffers Count RNBC (040A0h; R) 13.7.34 Receive Undersize Count RUC (040A4h; R) 13.7.35 Receive Fragment Count RFC (040A8h; R) 13.7.36 Receive Oversize Count ROC (040ACh; R) 13.7.37 Receive Jabber Count RJC (040B0h; R) 13.7.38 Management Packets Received Count1 MGTPRC (040B4h; R) 13.7.39 Management Packets Dropped Count MGTPDC (040B8h; R) 13.7.40 Management Pkts T ransmitted Count MGTPTC (040BCh; R) 13.7.41 Total Octets Received 13.7.42 Total Octets Transmitted TOTL (040C8h; R/W / TOTH (040CCh; R) 13.7.43 Total Packets Received TPR (040D0h; R) 13.7.44 Total Packets Transmitted TPT (040D4h; R) 13.7.45 Packets Transmitted (64 Bytes) Count PTC64 (040D8h; R) 13.7.46 Packets Transmitted (65-127 Bytes) Count PTC127 (040DCh; R) 13.7.47 Packets Transmitted (128-255 Bytes) Count PTC255 (040E0h; R) 13.7.48 Packets Transmitted (256-511 Bytes) Count PTC511 (040E4h; R) 13.7.49 Packets Transmitted (512-1023 Bytes) Count PTC1023 (040E8h; R) 13.7.50 Packets Transmitted (1024 Bytes or Greater) Count PTC1522 (040ECh; R) 13.7.51 Multicast Packets Transmitted Count MPTC (040F0h; R) 13.7.52 Broadcast Packets Transmitted Count BPTC (040F4h; R) 13.7.53 TCP Segmentation Context Transmitted Count TSCTC (040F8h; R) 13.7.54 TCP Segmentation Context Transmit Fail Count TSCTFC (040FCh; R) 13.8 Diagnostics Registers 13.8.1 Receive Data FIFO Head Register RDFH (02410h; R/W) 13.8.2 Receive Data FIFO Tail Register RDFT (02418h; R/W) 13.8.3 Receive Data FIFO Head Saved Register RDFHS (02420h; R/W) 13.8.4 Receive Data FIFO Tail Saved Register RDFTS (02428h; R/W) 13.8.5 Receive Data FIFO Packet Count RDFPC (02430h; R/W) 13.8.6 Transmit Data FIFO Head Register TDFH (03410h; R/W) 13.8.7 Transmit Data FIFO Tail Register TDFT (03418h; R/W) 13.8.8 Transmit Data FIFO Head Saved Register TDFHS (03420h; R/W) 13.8.9 Transmit Data FIFO Tail Saved Register TDFTS (03428h; R/W) 13.8.10 Transmit Data FIFO Packet Count TDFPC (03430h; R/W) 13.8.11 Packet Buffer Memory PBM (10000h - 1FFFCh; R/W) Page General Initialization and Reset Operation 14 14.1 Introduction 14.2 Power Up State 14.3 General Configuration 14.4 Receive Initialization 14.5 Transmit Initialization Page Software Developers Manual 375 Note: IPGR1 and IPGR2 are not needed in full duplex, but are easier to always program to the values shown. Table 14-1. Signal Descriptions 376 14.5.1 Signal Interface Software Developers Manual 377 Table 14-2. Signal Functions 14.5.2 GMII/MII Features not Supported Table 14-3 lists the signals and functions not provided by this interface. 14.5.3 Avoiding GMII Test Mode(s) 14.5.4 MAC Configuration 14.5.5 Link Setup 14.6 PHY Initialization (10/100/1000 Mb/s Copper Media) 14.7 Reset Operation Page Page 14.8 Initialization of Statistics Diagnostics and Testability 15 15.1 Diagnostics 15.1.1 FIFO State 15.1.2 FIFO Data 15.1.3 Loopback 15.2 Testability 15.2.1 EXTEST Instruction 15.2.2 SAMPLE/PRELOAD Instruction 15.2.3 IDCODE Instruction 15.2.4 BYPASS Instruction Page Appendix (Changes From 82544EI/82544GC) A A.1 Introduction A.2 New Features 390 A.3 Register Changes Table A-1 lists the registers that have been added or changed in the Ethernet controller. Table A-1. Register Changes Appendix B.1 Introduction B.2 82540EP/EM Differences B.2.2 No TBI/Internal SerDes Interface B.2.3 Single-Port Functionality B.2.4 32-Bit PCI Support