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Table 13-36. PHY Port Control Register Bit Description

Field	Bit(s)	Description	Mode	HW Rst	SW Rst

		Force MDI-X mode. Valid only when
		operating in manual mode. (PHY
MDI-X Mode	13	register 18, bit 12 = 0b.	R/W	0b	0b
MDI-X Mode	13	1b = MDI-X (cross over).	R/W	0b	0b
		1b = MDI-X (cross over).
		0b = MDI (no cross over).

Reserved	14	Always read as 0b. Write to 0b for	R/W	0b	0b
Reserved	14	normal operation.	R/W	0b	0b
		normal operation.

		This configuration bit is used to enable
		the Ethernet controller to drive its
		differential transmit clock out through
		the appropriate Analog Test (ATEST+/-)
		output pads. This feature is required in
		order to demonstrate conformance to
		the IEEE Clause 40 jitter specification.
		When high, it sends Jitter Test Clock
		out.
Jitter Test Clock	15	This bit works in conjunction with	R/W	0b	0b
		This bit works in conjunction with
		internal PHY register 18, bit 15. In order
		to have the clock probed out, it is
		required to perform the following write
		sequence:
		PHY register 18, bit15 = 1b
		PHY register 31 = 4000h (page select)
		PHY register 17 = 0080h
		PHY register 31 = 0000h (page select)

1.The default for this bit is determined by EEPROM configuration bits. If EEPROM bit NCSCRAMB is asserted, then the default is set to 1b.

13.4.7.1.16PHY Interrupt Status Register

PINTS (19d; R)

Table 13-37. PHY Interrupt Status Bit Description

268	Software Developer’s Manual

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