Intel PCI-X manual PCI Power Management Registers, Capability ID Byte Offset = 0 RO

Power Management

6.3.3PCI Power Management Registers

Power Management registers are part of the capabilities linked list pointed to by the Capabilities Pointer (Cap_Ptr) in the PCI configuration space. Refer to Section 4.1.

All fields are reset by LAN_PWR_GOOD. All of the fields except PME_En and PME_Status are reset by the deassertion (rising edge) of RST#. If AUX_POWER = 0b, the PME_En and PME_Status fields also reset by the deassertion (rising edge) of RST#.

The following table lists the organization of the PCI Power Management Register Block:

Byte Offset	Byte 3		Byte 2	Byte 1	Byte 0
DCh	Power Management Capabilities			Next Item Ptr	Capability ID
		(PMC)
			PMCSR_BSE	Power Management Control / Status
E0h	Data		Bridge Support
				Register (PMCSR)
			Extensions

The following sections describe the register definitions, whether they are required or optional for compliance, and how they are implemented in the Ethernet controller. Complete details can be found in the PCI Power Management Interface specification.

Note: The offset indicated is the byte-offset from the position indicated by Cap_Ptr in the Configuration Space Header.

6.3.3.1Capability ID

1 Byte Offset = 0 (RO)

Bits	Default	R/W	Description
07:00	01h	Read	ID – The Ethernet controller returns a value of 01h for this field, indicating
		Only	the linked list item as being the PCI Power Management Registers.

6.3.3.2Next Item Pointer

1 Byte Offset = 1 (RO)

Bits	Default	R/W	Description
		Read	Next Item Pointer - This field provides an offset into the function’s PCI
07:00	E4h		Configuration Space pointing to the location of next item in the function’s
		Only
			capability list. Its value of E4h points to the PCI-Xacapability.

a.Not applicable to the 82541xx, 82547GI/EI, or 82540EP/EM.

Software Developer’s Manual 137