Register Descriptions

13.4.7.1.23Extended PHY Specific Control Register 2 EPSCON2 (26d; R/W)

Table 13-47. Extended PHY Specific Control Register 2 Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

Fiber Output

 

111b = 1.2, 100b = 0.9, 001b = 0.6

 

 

 

2:0

110b = 1.1, 011b = 0.8, 000b = 0.5

R/W

100b

Retain

Amplitude

 

101b = 1.0, 010b = 0.7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

3

Reserved. Should be set to 1b.

R/W

1b

1b

 

 

 

 

 

 

Reserved

4

Reserved. Should be set to 0b.

R/W

0b

0b

 

 

 

 

 

 

Fiber Output

5

1b= 75 ohm.

R/W

0b

Update

Impedance

0b = 50 ohm.

 

 

 

 

 

 

 

 

 

 

Fiber Input

6

1b = 75 ohm.

R/W

0b

Update

Impedance

0b = 50 ohm.

 

 

 

 

 

 

 

 

 

 

Reserved

15:7

Reserved. Should be set to 0b.

R/W

000h

000h

 

 

 

 

 

 

NOTE: Not applicable to the 82540EP/EM, 82544GC/EI, 82541xx, or 82547GI/EI.

13.4.7.1.24Extended PHY Specific Status Register (82544GC/EI Only) EPSSTAT (27d; R)

Table 13-48. Extended PHY Specific Status Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

MODE[3:0]

27.3:0

MODE[3:0].

RO

MODE[3:0]

Retain

 

 

 

 

 

 

Reserved

27.15:4

Reserved. Should be set to

RO

0b

0b

000000000000b.

 

 

 

 

 

 

13.4.7.1.25MDI Register 30 Page Select1 R30PS (29d; WO)

Table 13-49. MDI Register 30 Page Select Bit Description

Field

Bit(s)

Description

Mode

HW Rst

SW Rst

 

 

 

 

 

 

Register 30 Page

15:0

Selects the register accessible via the

R/W

0000h

0000h

Select

“window” at MDI register 30.

 

 

 

 

 

 

 

 

 

 

1.Not applicable to the 82544GC/EI, 82541xx, or 82547GI/EI.

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Intel PCI-X, Intel Gigabit Ethernet Controllers manual Software Developer’s Manual 277