Register Descriptions

 

 

 

 

 

Field

Bit

Initial

 

Description

Value

 

 

 

 

 

 

 

 

 

 

 

 

Request EEPROM Access

EE_REQ

61

0b

The software must write a 1b to this bit to get direct EEPROM

 

 

 

access. It has access when EE_GNT is 1b. When the software

 

 

 

completes the access it must write a 0b.

 

 

 

 

EE_GNT

71

0b

Grant EEPROM Access

When this bit is 1b the software can access the EEPROM using the

 

 

 

SK, CS, DI, and DO bits.

 

 

 

 

 

 

1b

EEPROM Present

EE_PRES

81

This bit indicates that an EEPROM is present by monitoring the

 

 

0b2

EEDO input for a active-low acknowledge by the serial EEPROM

 

 

 

during initial EEPROM scan. 1b = EEPROM present.

 

 

 

 

 

 

 

EEPROM Size

 

 

 

0b

= 1024-bit (64 word) NM93C46 compatible EEPROM

EE_SIZE

91

0b

1b

= 4096-bit (256 word) NM93C66 compatible EEPROM

 

 

 

This bit indicates the EEPROM size, based on acknowledges seen

 

 

 

during EEPROM scans of different addresses. This bit is read-only.

 

 

 

Note: This is a reserved bit for the 82541xx and 82547GI/EI.

 

 

 

 

 

 

 

EEPROM Size (82541xx and 82547GI/EI)

 

 

 

For Microwire EEPROMs:

EE_SIZE

101

 

0b

= 6-bit addressable (64 words).

0b

1b

= 8-bit addressable (256 words).

 

 

 

For SPI EEPROMs:

 

 

 

0b

= 8-bit addressable.

 

 

 

1b

= 16-bit addressable.

 

 

 

 

Reserved

12:11

00b

Reserved

Should be written with 0b to ensure future compatibility. Reads as

 

 

 

0b.

 

 

 

 

 

 

 

 

EEPROM Type: Reflects the EE_MODE pin. (82541xx and

EE_TYPE

131

1b

82547GI/EI)

0b

= Microwire.

 

 

 

 

 

 

1b

= SPI.

 

 

 

 

Reserved

31:14

0b

Reserved

Should be written with 0b to ensure future compatibility. Reads as

 

 

 

0b.

 

 

 

 

 

 

1.Not applicable to the 82544GC/EI.

2.82541xx and 82547GI/EI only.

This register provides software direct access to the EEPROM. Software can control the EEPROM by successive writes to this register. Data & address information is clocked into the EEPROM by software toggling the EESK bit (2) of this register with EECS set to 1b. Data output from the EEPROM is latched into bit 3 of this register via the internal 62.5 MHz clock and can be accessed by software via reads of this register.

Note: Attempts to write to the FLASH device when writes are disabled (FEW = 01b) should not be attempted. Behavior after such an operation is undefined, and can result in component and/or system hangs.

Software Developer’s Manual

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Intel PCI-X, Intel Gigabit Ethernet Controllers manual Eereq, Eegnt, Eepres, Eesize, Eetype