Intel Intel Gigabit Ethernet Controllers, PCI-X manual Reset Operation, Lanpwrgood

General Initialization and Reset Operation

Once link is achieved by the PHY, software is notified when a Link Status Change (LSC) interrupt is generated by the Ethernet controller. This only occurs if software enabled the LSC bit in the Interrupt Mask Set/Read (MS) Register.

14.7Reset Operation

The following reset signals affect the Ethernet controller in different ways. RST# is the only external signal. Other reset events are asserted by performing slave writes to specific bits in the control registers.

Values indicated as “?” imply the default value is either unknown or is read from the EEPROM.

Note: In situations where the TX block is reset, the TX data lines are forced to all 0b’s. This causes a substantial number of symbol errors to be detected by the link partner. In TBI mode (82544GC/ EI)/internal SerDes (82546GB/EB and 82545GM/EM), if the duration is long enough, the link partner can restart the Auto-Negotiation process by sending “break-link” (/C/ codes with the configuration register value set to all 0b’s).

LAN_PWR_GOOD:

Deasserting LAN_PWR_GOOD resets all resettable registers in the Ethernet controller. The signal is level-sensitive, and the Ethernet controller is held in reset until LAN_PWR_GOOD is asserted. While asserted, all PCI signals are forced to a high impedance state.

General Registers:	Reset to power-on values.
Interrupt Registers:	Reset to power-on values.
Receive Registers:	Reset to power-on values (exceptions are the RAH/RAL, MTA, VFTA
	and RDBAH/RDBAL registers, which are not reset to any preset
	value. The valid bit of the RAH register is cleared).
Transmit Registers:	Reset to power-on values (exceptions are the TDBAH/TDBAL regis-
	ters, which are not reset to any preset value).
Statistics Registers:	Reset to power-on values.
Wakeup Registers:	The WUC (except for the PME_En and PME_Status bits if
	AUX_POWER = 1b), WUFC, IPAV, and FFLT registers are reset to
	their default value.
Diagnostic Registers:	Reset to power-on values (exception is the PBM memory, which is not
	reset to any preset value).
PCI Config Space:	Context Lost; requires initialization.
PHY:	RST# is asserted to reset the PHY while LAN_PWR_GOOD is deas-
	serted.

In addition, the Ethernet controller automatically reads certain values from the EEPROM and configures itself to use those EEPROM settings.

Software Developer’s Manual 381