Intel PCI-X manual GPI to SDP Bit Mappings, Vreg Power, Down, Linkmode

			Register Descriptions
Field	Bit(s)	Initial	Description
		Value
			Voltage Regulator Power Down (82541xx and 82547GI/EI only)
			0b = Normal operation.
VREG POWER	21	0b	1b = Voltage regulators power down.
DOWN			This bit is initialized from the EEPROM.
			Note: This is a reserved bit for all remaining Ethernet controllers.
			Set to 0b.
			Link Mode. This controls which interface is used to talk to the link.
			00b = Direct copper (1000Base-T) interface (GMII/MII internal PHY
			mode)
LINK_MODE	23:22	0b	01b = Reserved
			10b = Direct Fiber interface (using internal SerDes)
			11b = external TBI interface
			Note: These are reserved bits for the 82540EP/EM, 82541xx, and
			82547GI/EI. Set to 00b
			Reserved
Reserved	31:24	0b	Should be written with 0b to ensure future compatibility.
			Reads as 0b.

1.These bits are read from the EEPROM

The Ethernet controller allows for up to two externally controlled interrupts. The upper two software-definable pins, SDP[7:6] (SDP[3:2] for the 82541xx and 82547GI/EI), can be mapped for use as GPI interrupt bits. These mappings are enabled by the SDPx_GPIEN bits only when these signals are also configured as inputs via SDPx_IODIR. When configured to function as external interrupt pins, a GPI interrupt is generated when the corresponding pin is sampled in an active-high state.

The bit mappings are shown in Table 13-11for clarity.

Table 13-11. GPI to SDP Bit Mappings

SDP pin to be used as		CTRL_EXT field settings		Resulting ICR bit
GPI				(GPI)
	Directionality		Enable as GPI interrupt
7	SDP7_IODIR		SDP7_GPIEN	14
21	SDP2_IODIR1		SDP2_GPIEN1
6	SDP6_IODIR		SDP6_GPIEN	13
31	SDP3_IODIR1		SDP3_GPIEN1

1.82541xx and 82547GI/EI only

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