Intel Intel Gigabit Ethernet Controllers, PCI-X manual Status Register Layout, 82547GI/EI

PCI Local Bus Interface

Bit(s)	Initial Value	Description
4	0b	Memory Write and Invalidate Enable (not
		applicable to the 82547GI/EI).
5	0b	Palette Snoop Enable.
6	0b	Parity Error Response (not applicable to the
		82547GI/EI).
7	0b	Wait Cycle Enable.
8	0b	SERR# Enable (not applicable to the 82547GI/EI).
9	0b	Fast Back-to-Back Enable.
10a	0b	Interrupt Disable (INTA# or CSA signaled).
15:10	0b	Reserved.
15:11a

a.82541xx and 82547GI/EI only.

Table 4-4. Status Register Layout

15 4 3 0

Status Bits

Reserved

Bit(s)	Initial Value	Description
3:0	0b	Reserved.
2:0a
		Interrupt Status. This bit is 1b when the Ethernet
3a		controller is generating an interrupt internally.
	0b	When Interrupt Disable in the Command Register
		is also cleared, the Ethernet controller asserts
		INTA# or signal an interrupt over CSA.
		New Capabilities: Indicates that an Ethernet
		controller implements Extended Capabilities. The
4	1b	Ethernet controller sets this bit and implements a
		capabilities list to indicate that it supports PCI
		Power Management, PCI-X Bus, and message
		signaled interrupts.
5	1b	66 MHz Capable (don’t care for the 82547GI/EI).
6	0b	UDF Supported. Hardwired to 0b for PCI 2.3a.
		Fast Back-to-Back CapableThis bit must be
7	0b	cleared to 0b in PCI-X mode (not applicable to the
		82547GI/EI).
8	0b	Data Parity Reported.
10:9	01b	DEVSEL Timing (indicates medium device). Not
		applicable to the 82547GI/EI.
11	0b	Signaled Target Abort.

78 Software Developer’s Manual