Intel PCI-X, Intel Gigabit Ethernet Controllers manual Ledactled

Register Descriptions

Table 13-43. SPEED_TEN_LED and LINK_ACT_LED Bit Description

		Disable the SPEED_TEN_LED
		Extension Logic.
		0b = Enable logic.
LED Stretch Disable	5	1b = Disable logic.	R/W	1b	1b
		Note: Only when both the stretch and
		blink are disabled the input bypasses
		the blink logic and is muxed out with no
		sampling (only combinational logic).
LED Source Select	9:6	Mux the designated input to	R/W	0001b	0001b
		LED_ACT_LED.
		Disable the LINK_ACT_LED Blink
LED Blink Disable	10	Logic.	R/W	1b	1b
		0b = Enable logic.
		1b = Disable logic.
		Disable the LINK_ACT_LED Extension
		Logic.
		0b = Enable logic.
LED Stretch Disable	11	1b = Disable logic.	R/W	0b	0b
		Note: Only when both the stretch and
		blink are disabled the input bypasses
		the blink logic and is muxed out with no
		sampling (only combinational logic).
Invert Select	12	When set to 1b, all LED outputs are	R/W	0b	0b
		inverted.
Reserved	14:13	Always read as 0b. Write to 0b for	R/W	00b	00b
		normal operation
		This bit is used to disable special power
Disable 10 Power		saving in 10BASE-T mode and parallel
	15	detection. When set to 1b, power	R/W	0b	0b
Saving
		reduction features of 10BASE-10 are
		disabled (reserved for customers).

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