Intel Intel Gigabit Ethernet Controllers, PCI-X manual 13 GC/EI GPI to SDP Bit Mapping, Spdbyps

Register Descriptions

Field	Bit(s)		Initial	Description
			Value
				Speed Select Bypass
				When set to 1b, all speed detection mechanisms are bypassed,
				and the Ethernet controller is immediately set to the speed
SPD_BYPS	15	0		indicated by CTRL.SPEED. This might be used to override the
				hardware clock switching circuitry and give full control to
				software. SPD_BYPS differs from the CTRL.FRCSPD function
				in that FRCSPD uses the internal clock switching circuitry rather
				than an immediate forcing function of the speed settings, as
				does SPD_BYPS.
				Invert Power State Bit 1
IPS1	16	0		Inverts the polarity of bit 1 of the PWR_STATE signal when set
				to 1b.
				Configurable through the EEPROM.
				Relaxed Ordering Disabled
				When set to 1b, the Ethernet controller does not request any
RO-DIS	17	0		relaxed ordering transactions in PCI-X mode regardless of the
				state of bit 1 in the PCI-X command register. When this bit is
				clear and bit 1 of the PCI-X command register is set, the
				Ethernet controller requests relaxed ordering transactions as
				described.
				Reserved
Reserved	31:18	0		Should be written with 0b to ensure future compatibility.
				Reads as 0b.
Table 13-13. 82544GC/EI GPI to SDP Bit Mapping

B_SDP	CTRL_EXT	CTRL_EXT	ICR
	(SWDPINHI)	(GPI_EN)	(GPI)
7	7	3	14
6	6	2	13
5	Reserved	Reserved	Reserved
4	4	0	11

Software Developer’s Manual 237