Receive Interrupt Absolute Delay Timer Radv

Receive and Transmit Description

Initial State
	Packet received &
	transferred to host
Idle	memory
	Restart Count
	Other receive	Restart Count
	timer interrupt	Restart Count
	Running	Packet received	&
		transferred to host
		memory
Generate	Timer expires
Int	Timer expires
Int

Figure 3-3. Packet Delay Timer Operation (State Diagram)

3.2.7.1.2Receive Interrupt Absolute Delay Timer (RADV)

The Absolute Timer ensures that a receive interrupt is generated at some predefined interval after the first packet is received. The absolute timer is started once a packet is received and transferred to host memory (specifically, after the last packet data byte is written to memory) but is NOT reinitialized / restarted each time a new packet is received. When the Absolute Timer expires (no receive interrupt has been generated for the amount of time defined in RADV) the Receive Timer Interrupt is generated.

Setting RADV to 0b or RDTR to 0b disables the Absolute Timer. To disable the Packet Timer only, RDTR should be set to RADV + 1b.

The Absolute Timer is reinitialized (but not started) when the Receive Timer Interrupt is generated due to a Packet Timer expiration or Small Receive Packet Detect Interrupt.

Software Developer’s Manual

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Image 43

Intel PCI-X manual Receive Interrupt Absolute Delay Timer Radv, Packet Delay Timer Operation State Diagram

Contents

82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, Software Developer’s Manual Initial Public Release Date Version Comments Software Developer’s Manual Contents TCP Segmentation Use of Multiple Data Descriptors Software Developer’s Manual Vii Power Management 129 Introduction to Power Management 10.1.3 203 13.4.25 13.7.10 Appendix 82540EP/EM and 82545GM/EM Differences Xiv Overview Scope Network Side Features Ethernet Controller FeaturesPCI Features CSA Features 82547GI/EI Only Host Offloading Features Additional Performance Features Technology Features Additional Ethernet Controller Features Register and Bit References ConventionsRelated Documents Memory Alignment Terminology Introduction Architectural Overview PHY External ArchitectureLAN a LAN B ECHO, Next Fext Eeprom FlashAGC, A/D 1 PCI/PCI-X Core Interface Microarchitecture DMA Engine and Data Fifo 2 82547GI/EI CSA Interface 5 MII/GMII/TBI/Internal SerDes Interface Block 4 10/100/1000 Mb/s Receive and Transmit MAC Blocks Eeprom Interface 6 10/100/1000 Ethernet Transceiver PHY Little Endian Data Ordering DMA AddressingFlash Memory Interface Example 2-1. Byte Ordering Intel Architecture Byte Ordering Ethernet AddressingIA Byte # LSB MSB Interrupts TCP Segmentation Hardware Acceleration CapabilityBuffer and Descriptor Structure Checksum Offloading Architectural Overview Packet Reception IntroductionPacket Address Filtering Receive Descriptor Format Receive Data StorageReceive Descriptor Rdesc Layout Receive Receive Descriptor Status FieldReceive Status RDESC.STATUS Layout PIF Ipcs Tcpcs RSV Ixsm EOP Receive Descriptor Errors Field CXE Receive Errors RDESC.ERRORS LayoutRXE IPE Tcpe RSV RSV SEQ PRI Receive Descriptor Special FieldSpecial Descriptor Field Layout PRI CFI Vlan Receive Descriptor Fetching Algorithm Receive Descriptor Fetching Null Descriptor Padding Receive Descriptor Write-BackReceive Descriptor Queue Structure Receive Descriptor Packing Receive Descriptor Ring Structure Receive Interrupt Delay Timer / Packet Timer Rdtr Receive Timer InterruptReceive Interrupts Packet Delay Timer Operation State Diagram Receive Interrupt Absolute Delay Timer Radv Small Receive Packet Detect Receiver Fifo Overrun 8 82544GC/EI Receive InterruptsReceive Packet Checksum Offloading Receive Descriptor Minimum Threshold ICR.RXDMT Packet Type HW IP Checksum HW TCP/UDP Checksum Calculation Supported Receive Checksum Capabilities Packet Type HW IP Checksum MAC Address FilterGC/EI Supported Receive Checksum Capabilities Packet Type HW IP Checksum HW TCP/UDP Checksum 9.4 IPv6 Filter Packet TransmissionSNAP/VLAN Filter 9.3 IPv4 Filter Transmit Descriptors Transmit Data Storage Transmit Descriptor Legacy Descriptions Transmit Descriptor Tdesc Layout Legacy ModeLegacy Transmit Descriptor Format Transmit Descriptor Tdesc Layout CSS Transmit Descriptor Description LegacyCMD STA Ifcs EOP Transmit Descriptor Command Field Format10. Transmit Command TDESC.CMD Layout IDE VLE Dext RSV 11. Transmit Status Layout Transmit Descriptor Status Field Format 12. Special Field TDESC.SPECIAL Layout Transmit Descriptor Special Field Format 5 TCP/IP Context Transmit Descriptor Format 13. Transmit Descriptor Tdesc Layout Type = 0000b 6 TCP/IP Context Descriptor Layout Transmit Description Descriptor Offload 14. Transmit Descriptor Tdesc Layout Dtyp 6.1 TCP/UDP Offload Transmit Descriptor Command FieldTransmit Description Tucmd IDE RSV Dext TSE TCP 15. Command Field TDESC.TUCMD Layout82544GC/EI only 6.2 TCP/UDP Offload Transmit Descriptor Status Field 7 TCP/IP Data Descriptor Format16. Transmit Status Layout Popts RSV STA Dcmd Dtyp Dtalen 17. Transmit Descriptor Tdesc Layout Type = 0001bPopts TSE Ifcs EOP 7.1 TCP/IP Data Descriptor Command Field18. Command Field TDESC.DCMD Layout IDE VLE Dext 19. Transmit Status Layout 7.2 TCP/IP Data Descriptor Status FieldReserved RSV Txsm Ixsm 7.3 TCP/IP Data Descriptor Option Field7.4 TCP/IP Data Descriptor Special Field 20. Packet Options Field TDESC.POPTS Layout 21. Special Field TDESC.SPECIAL Layout Transmit Descriptor Ring Structure Transmit Descriptor Ring Structure Transmit Descriptor Write-back Transmit Descriptor Fetching Transmit Interrupts Delayed Transmit Interrupts Transmission Process Assumptions TCP/UDP Data FCS TCP Segmentation PerformancePacket Format TCP Segmentation Data Fetch Control 3936 TCP Segmentation Indication TCP Partial Pseudo-Header Checksum TCP Segmentation Use of Multiple Data Descriptors Version IP Hdr IP and TCP/UDP HeadersOptions Fragment Offset Low Type of service Version IP Hdr Length FragmentOffset High Header Checksum Byte1 Byte0 Destination Port Destination Port Sequence NumberTCP Header Length Checksum Urgent Pointer Options Byte3 Byte2 Byte1 Byte0 Source Port Destination Port Length Checksum Transmit Checksum Offloading with TCP Segmentation 17. UDP Pseudo Header Diagram for IPv4 9 IP/TCP/UDP Header Updating 19. Overall Data Flow 9.2 TCP/IP/UDP Header for the Subsequent Frames 9.1 TCP/IP/UDP Header for the First Frame 9.3 TCP/IP/UDP Header for the Last Frame IP/TCP/UDP Transmit Checksum Offloading Ipcss Receive and Transmit Description PCI PCI ConfigurationMandatory PCI Registers Address Description Specification Update for the latest stepping information Addr Base Address Registers Field Bits Read Initial Description Write Value All base address registers have the following fields Offset Space Expansion ROM Base Address Address Next Pointer Capabilities Linked List Bits Initial Value Description PCI definition for more details 82547GI/EI Status Register Layout Byte Offset PCI-X Configuration RegistersPCI-X Capability ID Next Capability Maximum Memory Read Byte Count. This register sets PCI-X CommandBits Read Initial Write Value USC SCD PCI-X StatusBits Read Intial Description Write Value Reserved and Undefined Addresses Command Register as follows Bits Read Initial Description Write Value 05h Message Signaled Interrupts1Message Signaled Interrupt Configuration Registers MSI Capability ID Message Control 3.1.6 Commands3.1.4 Message Address 3.1.5 Message Upper Address Transaction Cause PCI Commands PCI-X Commands Accepted PCI/PCI-X Command as a TargetPCI Commands Abr PCI-X Commands Transaction Target PCI Commands PCI-X Commands Memory Write Operations PCI/PCI-X Command Usage MWI Bursts Master Write Command Usage Algorithm Rules for Memory Read Operations PCI-X Command UsageMemory Read Operations MW Bursts Outstanding Memory Read Cache Line Information1 Interrupt Assignment 82547GI/EI Only LAN DisableTarget Transaction Termination CardBus Application 82541PI/GI/EI Only General Overview Eeprom Interface Component Identification Component Identification Via Programming InterfaceStepping Vendor ID Device ID Description Eeprom Device and Interface Signature and CRC Fields Software Access Command Line Parameters Eeupdate Utility For the 82541xx and 82547GI Eeprom Address Map1Ethernet Controller Address Map Word Used Bit Image 82546GB/EB only LAN a82545GM 82540EP 82541xx and 82547GI/EI only 82545GM 82541xx ASF 82540EP/EM GC/EI and 82541ER Eeprom Address Map Word Description Default HW AccessAddress Hi Byte Low Byte Bit Name Description Ethernet Address Words 00h-02hSoftware Compatibility Word Word 03h Software Compatibility Word Word 03h PBA Number Word 08h, 09h SerDes Configuration Word 04hEeprom Image Version Word 05h Compatibility Fields Word 05h 07h Initialization Control Word 1 Word 0Ah Initialization Control Word 1 Word 0Ah Subsystem Vendor ID Word 0Ch Subsystem ID Word 0Bh Initialization Control Word 2 Word 0Fh Device ID Word 0Dh, 11h1Vendor ID Word 0Eh Initialization Control Word 2 Word 0Fh 82541PI/GI Only OEM Reserved Words Words 10h, 11h, 13h 1Fh Common Power Word 12hSoftware Defined Pins Control Word 10h1, 20h PHY Register Address Data Words 10h, 11h, and 13h 1Eh Software Defined Pins Control Word 10h, 20h CSA Port Configuration 2 Word 21h CSA Port Configuration 2 Word 21hBit Description Default Reserved Words 23h 2Eh 20 D0 Power Word 22h high byte21 D3 Power Word 22h low byte Circuit Control Word 21h Management Control Word 13h1, 23h2 10. Initial Management Control Register Settings82541PI/GI/EI and 82547GI/EI Only 11. SMBus Slave Address SMBus Slave Address Word 14h1 low byte, 24h low byte For Address 24h High Byte / LAN a Initialization Control 3 Word 14h1 high byte, 24h high byte12. Initialization Control 82546GB/EB uses INTB# 28 IPv6 Address words 17h 1Eh1 and 27h 2Eh LED Configuration Defaults Word 2Fh2Boot Agent Main Setup Options Word 30h 27 IPv4 Address Words 15h 16h1 and 25h 26h 15. Boot Agent Main Setup Options DBS Boot Agent Configuration Customization Options Word 31hBBS DFU 16. Boot Agent Configuration Customization Options Word 31hSIG Mode 17. Boot Agent Configuration Customization Options Word 32h Boot Agent Configuration Customization Options Word 32h IBA Capabilities Word 33h IBA Secondary Port Configuration Words 34h-35h18. IBA Capabilities Eeprom Images 19. WOL Mode and Functionality Word 0Ah20. WOL Mode and Functionality Word 20h Checksum Word Calculation Word 3Fh Number Parallel Flash Memory21. Flash Memory Manufacturers Manufacturer 124 Flash Interface Operation Flash Control and Accesses Write Accesses Read Accesses Flash Buffer Write Cycle 128 Assumptions Introduction to Power Management D3cold support Power States 1.2 D0u State Dr State 1.3 D0a D0 active Timing1.4 D3 Diagram # Power Up Off to Dr to D0u to D0a Transition from D0a to D3 and Back Without PCI Reset Transition From D0a to D3 and Back Without PCI Reset RST# Transition From D0a to D3 and Back with PCI Reset PCI Reset Sequence PCI Reset Without Transition to D3 Next Item Pointer Byte Offset = 1 RO PCI Power Management RegistersBits Default Description Capability ID Byte Offset = 0 RO Reserved Power Management Capabilities PMC 2 Bytes Offset = 2 ROEeprom Software Developer’s Manual 139 Byte Offset = 7 RO Pmcsrbse Bridge Support Extensions3.6 Data Register Byte Offset = 6 RO Wakeup Advanced Power Management Wakeup Acpi Power Management Wakeup Pre-Defined Filters Wakeup PacketsDirected Exact Packet Offset Field Value Action Comment 3.1.3 BroadcastDirected Multicast Packet 3.1.4 Magic Packet*1 Offset Field Value Action Comment Bytes ARP 3.1.5 ARP/IPv4 Request Packet1+ S a + D + S a Offset # of bytes Field Value Action Comment Directed IPv4 Packet1 Directed IPv6 Packet1 + D + S IPX Diagnostic Responder Request Packet Example1Flexible Filter + S 3.4 IPv6 Neighbor Discovery Filter1 Directed IPX Packet Example CRC Wakeup Packet Storage 152 Link Interfaces Overview Ethernet Interface 1.2 8B10B Encoding/Decoding Internal SerDes Interface/TBI Mode- 1Gb/s1 Code OrderedSet Gmii 1 Gb/sCode Groups and Ordered Sets Code Group and Ordered Set Usage Duplex Operation Internal Interface1MII 10/100 Mb/s Half Duplex Full Duplex Packet Bursting Carrier Extension 1000 Mb/s Only Auto-Negotiation and Link Setup2 Auto-Negotiation and Link Setup1 Link Speed Link Configuration in Internal Serdes/TBI Mode1Auto-Negotiation Hardware Auto-Negotiation TXCW.txConfigWord Bit Description Software Auto-Negotiation Forcing Link Internal GMII/MII Mode Forcing Speed Using Auto-Speed Detection ASD Comments Regarding Forcing Link Automatic Detection of Link Speed using SPD-INDDuplex MII Management Registers Control Bit Effect on Control Bits Internal SerDes Mode1 Control Bit ResolutionInternal Serdes Mode1 Hardware Enabled Internal Serdes1 Mode Software Enabled GMII/MII Mode PHY Speed Indication Internal PHY Mode Control Bit ResolutionInternal Serdes Mode1 Auto-Negotiation Skipped GMII/MII Mode Force Speed GMII/MII Mode Auto-Speed Detection GMII/MII Mode Force Link Loss of Signal/Link Status IndicationInternal Serdes Mode Internal PHY Mode Adaptive IFS1 10/100 Mb/s Specific Performance Enhancements Register Name Description Flow ControlMAC Control Frames & Reception of Flow Control Packets 10. Flow Control Registers 3x MAC Control Frame Format Transmission of Pause Frames Discard Pause Frames and Pass MAC Control Frames External Control of Flow Control Operation1 Software Initiated Pause Frame Transmission Packet #Octets 802.1q Vlan Packet Format1 802.1q Tagged Frames Vlan Packet Format Comparison Stripping 802.1q Tags on Receives Transmitting and Receiving 802.1q Packets802.1q Vlan Packet Filtering Adding 802.1q Tags on Transmits VFE Packet Reception Decision Table 178 Selecting an LED Output Source Configurable LED Outputs1 Blink Control Polarity Inversion Blink Control 182 Auto-Negotiation PHY Functionality and Features Next Page Exchanges Register Update 1000BASE-T 11.2 MDI/MDI-X Crossover copper onlyStatus Pin 11.2.2 10/100 Downshift 82540EP/EM Only Polarity Correction copper only Cable Length Detection copper only PHY Power Management copper onlyLink Down Energy Detect copper only 11.4.4 D3 Link-Up, Speed-Management Disabled copper only 11.4.3 D3 Link-Up, Speed-Management Enabled copper only11.4.2 D3 State, No Link Required copper only Initialization Mdio Control Mode Overview of Link Establishment Determining Link State Determining Duplex State Via Parallel Detection Configuration ResultFalse Link Forced Operation 11.7.1 1000BASE-T Link CriteriaAuto Negotiation Parallel Detection SmartSpeed Using SmartSpeedLink Enhancements 11.7.3 10BASE-T Management Data Interface Low Power OperationPause And Asymmetric Pause Settings Asmdir Settings Pause Setting Smart Power-Down Powerdown via the PHY Register11.11 1000 Mbps Operation DSP ECHO, Next 4DPAM5 Transmit Fifo Transmit Functions Transmit/Receive Flow Spectral ShaperLow-Pass Filter Line Driver Receive Functions Viterbi Decoder/Decision Feedback Equalizer DFE 11.12 100 Mbps Operation11.13 10 Mbps Operation Descrambler PHY Line Length Indication 202 Introduction1 Features of Each MAC12.2.1 PCI/PCI-X interface 204 12.2.3 SDP, LED, INT# output MAC Configuration Register SpaceIO BAR Eeprom Map Shared EepromEeprom Arbitration Shared Flash Flash Access Contention Pin sampled LAN device controlled Enable/Disable Values Sampled on Reset Multi-Function Advertisement Power ReportingInterrupt Use INTA# EnabledSummary Interrupt Line Used Register Conventions Register Descriptions Memory and I/O Address Decoding Memory-Mapped Access to Internal Registers and MemoriesMemory-Mapped Access to Flash Memory-Mapped Access to Expansion ROM Ioaddr IoaddrIodata Offset Abbreviation Name Size AD C/BE#30 Bits Iodata Register Configurations 82547GI/EI only Ethernet Controller Register SummaryCategory Offset Abbreviation Name 82544GC/EI Ipat 82544GC Gprc XofftxcFcruc PRC64 To the 82544GC/EI , 82541xx , or 82547GI CategoryAbbreviation Name Register 82544GC/EI , 82541xx , or 82547GI/EI PCI-X Register Access Split1 Device Control Register Main Register DescriptionsCtrl 00000h R/W Field Bits Initial Description Value Ctrl Register Bit Description Ilos SLUSpeed ADVD3WUC FrcdplxSDP0DATA SDP1DATA Field Bits Initial Description Little-Endian Data Ordering BEM = 0 64-bit mode Little-EndianDevice Status Register Status 00008h R Txoff Status Register Bit DescriptionTbimode Pcixspd AsdvPCI66 Pcixmode 82544GC/EI Only EEPROM/Flash Control & Data RegisterEecd 00010h R/W Eecd Register Bit Description Eesize EereqEegnt Eepres Eerd 00014h RW Eeprom Read Register1Eeprom Read Register Bit Description Done Start Eeprom Read Register Bit Description 82541xx and 82547GI/EI Flash Access FLA Flash Access1FLA 0001Ch R/W 23 16 Extended Device Control RegisterCtrlext 00018h, R/W 10. Ctrlext Register Bit Description Asdchk SDP6IODIRSDP2IODIR SDP7IODIR Linkmode Vreg Power11. GPI to SDP Bit Mappings Down CTRL.RST Swdpinshi12 GC/EI Ctrlext Register Bit Description Swdpiohi 13 GC/EI GPI to SDP Bit Mapping Mdic 00020h R/W MDI Control Register Phyadd 14. MDI Control Register Bit DescriptionRSV PHY REG Data Regadd Register Mode Description 15. PHY Register Bit Mode DefinitionsPHY Registers MSB Field Bits Description Mode HW Rst SW Rst 242 LSB Enaxc RO,L Software Developer’s Manual 245 246 For the 82541xx and 82547GI/EI Pause 82544GC/EI only 82541xx 82541xx 82547GI/EI 82541xx and 82547GI/EI only RF1 82544GC/EI OnlyANEG3 ANEG2 Software Developer’s Manual 251 23. Link Partner Ability Register Base Page Bit Description1 100BASE-TX 82541xx and 82547GI/EI Only24. PHY Link Page Ability Bit Description1 10BASE-T 1b 82541xx Software Developer’s Manual 255 Bits Field Description Mode HW Rst SW Rst ANEG1 MasterANEG0 MASTER/SLAVE 258 Software Developer’s Manual 259 DIS NLP SFD Preen Software Developer’s Manual 263 264 Software Developer’s Manual 265 266 82541/GI/ER and 82547GI B1 82541EI/82547GI B0 stepping 268 HCD NOK Software Developer’s Manual 271 272 Field Bits Description Mode HW Rst Ledactled SPEED1000LED SPEED100LED 276 Software Developer’s Manual 277 51. MDI Register 30 Operations Documented MDI Register 30 Operations1To Perform Operation MDI Read/Write Sequence Fcah 0002Ch R/W Flow Control Address LowFlow Control Address High Fcal 00028h R/W VET 00038h R/W Flow Control TypeVlan Ether Type FCT 00030h R/W 57. Fcttv Register Bit Description Flow Control Transmit Timer ValueFcttv 00170h R/W 56. VET Register Bit Description Txcw 00178h R/W Transmit Configuration Word Register158. Txcw Register Bit Description Rxcw 00180h R Receive Configuration Word Register1 59. Rxcw Register Bit Description LED1 ACTIVITY# LED0 LINKUP# LED Control1Ledctl 00E00h RW ANC 60. LED Control Bit Description1 Mode Encodings for LED Outputs1 Mode Pneumonic State / Event Indicated 61. Mode Encodings for LED Outputs Field Bits Initial Value Description Packet Buffer AllocationPBA 01000H R/W 62. PBA Register Bit Description ICR 000C0H R Interrupt Cause Read Register63. ICR Register Bit Description GPISDP6 RXT0Mdac Rxcfg ITR 000C4h R/W Interrupt Throttling Register1Interval ICS 000C8h W Interrupt Cause Set Register64. ICS Register Bit Description To the 82544GC/EI Interrupt Mask Set/Read RegisterIMS 000D0h R/W 65. IMS Register Bit Description IMC 000D8h W Interrupt Mask Clear Register 66. IMC Register Bit Description SBP Receive Control RegisterRctl 00100h R/W 67. Rctl Register Bit Description Rdmts MPELPE LBM Cfien BAMBsize VFE Bsex PmcfSecrc 68. Fcrtl Register Bit Description XON Enable 82544GC/EI , 82541xx , and 82547GI/EI onlyFlow Control Receive Threshold Low Fcrtl 02160h R/W Fcrth 02168h R/W Flow Control Receive Threshold High69. Fcrth Register Bit Description Rdbah 02804h R/W Receive Descriptor Base Address LowReceive Descriptor Base Address High Rdbal 02800hR/W RDH 02810h R/W Receive Descriptor LengthReceive Descriptor Head Rdlen 02808h R/W Rdtr 02820h R/W Receive Delay Timer RegisterReceive Descriptor Tail RDT 02818hR/W Radv 0282Ch RW Receive Interrupt Absolute Delay Timer1 Tctl 00400hR/W Receive Small Packet Detect Interrupt1Transmit Control Register Rsrpd 02C00h R/W TCTL.COLD 76. Tctl Register Bit DescriptionCold PSP Nrtu Transmit IPG RegisterTipg 00410R/W Rtlc IPGR2 IPGR1 Ipgt 77. Tipg Register Bit Description Aifs 00458R/W Adaptive IFS Throttle AITIPGR2 79. Tdbal Register Bit Description Transmit Descriptor Base Address LowTdbal 03800h R/W 78. Aifs Register Bit Description Tdlen 03808h R/W Transmit Descriptor Base Address HighTransmit Descriptor Length Tdbah 03804h R/W TDH 03810h R/W Transmit Descriptor Head82. TDH Register Bit Description Tidv 03820h R/W Transmit Interrupt Delay ValueTransmit Descriptor Tail TDT 03818h R/W Txdctl 03828h R/W TX DMA Control 82544GC/EI onlyTransmit Descriptor Control Txdmac 03000h R/W Lwthresh RSV1 Gran RSV Wthresh Hthresh Pthresh 86. Txdctl Register Bit Description Lwthresh Transmit Absolute Interrupt Delay Value1Tadv 0382Ch RW Gran Tspbp Tsmt TCP Segmentation Pad And Minimum Threshold Tspmt 03830h RWTspbp Software Developer’s Manual 319 Wthresh RSV Hthresh Pthresh Receive Descriptor ControlRxdctl 02828h R/W 87. Rxdctl Register Bit Description 3111 Receive Checksum ControlRxcsum 05000h R/W 88. Rxcsum Register Bit Description Tuofld IpofldIPV6OFL 89. MTA Register Bit Description Filter RegistersMulticast Table Array MTA1270 05200h-053FCh R/W Destination Address RAH 05404h + 8∗n R/W Receive Address LowReceive Address High RAL 05400h + 8*n R/W RAH Vlan Filter Table Array1VFTA1270 05600h 057FCh R/W 91. RAH Register Bit Description 92. VFTA1270 Bit Description Wakeup RegistersWakeup Control Register WUC 05800h R/W SPM Wakeup Filter Control RegisterWufc 05808h R/W Apmpme WUS 05810h R Wakeup Status Register 330 Ipav 5838h R/W IP Address Valid Field Dword # Address Bits Initial Value Description 13.6.5 IPv4 AddressIP4AT 05840h 05858h R/W2 Address Dword # Address Bits Initial Value Description 13.6.6 IPv6 AddressIP6AT 05880h 0588Ch R/W IPV6ADDR0 Wakeup Packet Memory 128 Bytes Wakeup Packet LengthFlexible Filter Length Table LEN2 Flexible Filter Mask Table Ffmt 09000h 093F8h R/WLEN0 LEN1 Flexible Filter Value Table Statistics RegistersFfvt 09800h 09BF8h R/W Algnerrc 04004h R CRC Error CountAlignment Error Count Crcerrs 04000h R Rxerrc 0400Ch R Symbol Error CountRX Error Count Symerrs 04008h R SCC 04014h R Missed Packets CountSingle Collision Count MPC 04010h R MCC 0401Ch R Excessive Collisions CountMultiple Collision Count Ecol 04018h R Colc 04028h R Late Collisions CountCollision Count Latecol 04020h R Tncrs 04034h R Defer CountTransmit with No CRS DC 04030h R Cexterr 0403Ch R Sequence Error CountCarrier Extension Error Count SEC 04038h R Xonrxc 04048h R Receive Length Error CountXON Received Count Rlec 04040h R Xoff Received Count XON Transmitted CountXoff Transmitted Count PRC64 0405Ch R FC Received Unsupported CountPackets Received 64 Bytes Count Fcruc 04058h R PRC255 04064h R Packets Received 65-127 Bytes CountPackets Received 128-255 Bytes Count PRC127 04060h R PRC1023 0406Ch R Packets Received 256-511 Bytes CountPackets Received 512-1023 Bytes Count PRC511 04068h R Gprc 04074h R Packets Received 1024 to Max Bytes CountGood Packets Received Count PRC1522 04070h R Mprc 0407Ch R Broadcast Packets Received CountMulticast Packets Received Count Bprc 04078h R Gorcl 04088h R/GORCH 0408Ch R Good Packets Transmitted CountGood Octets Received Count Gptc 04080h R Rnbc 040A0h R Good Octets Transmitted CountReceive No Buffers Count Gotcl 04090h R/ Gotch 04094 R RFC 040A8h R Receive Undersize CountReceive Fragment Count RUC 040A4h R RJC 040B0h R Receive Oversize CountReceive Jabber Count ROC 040ACh R Mgtprc 040B4h R Management Packets Received Count1129. RJC Register Bit Description Management Pkts Transmitted Count1 Management Packets Dropped Count1Total Octets Received 131. Totl and Toth Register Bit Descriptions Total Octets TransmittedTotl 040C8h R/W / Toth 040CCh R 130. Torl and Torh Register Bit Descriptions TPT 040D4h R Total Packets ReceivedTotal Packets Transmitted TPR 040D0h R PTC127 040DCh R Packets Transmitted 64 Bytes CountPackets Transmitted 65-127 Bytes Count PTC64 040D8h R PTC511 040E4h R Packets Transmitted 128-255 Bytes CountPackets Transmitted 256-511 Bytes Count PTC255 040E0h R PTC1522 040ECh R Packets Transmitted 512-1023 Bytes CountPackets Transmitted 1024 Bytes or Greater Count PTC1023 040E8h R Bptc 040F4h R Multicast Packets Transmitted CountBroadcast Packets Transmitted Count Mptc 040F0h R Tsctfc 040FCh R TCP Segmentation Context Transmitted CountTCP Segmentation Context Transmit Fail Count Tsctc 040F8h R Rdfh 02410h R/W Diagnostics RegistersReceive Data Fifo Head Register Receive Data Fifo Tail Register Rdfts 02428h R/W Receive Data Fifo Head Saved RegisterReceive Data Fifo Tail Saved Register Rdfhs 02420h R/W Tdfh 03410h R/W Receive Data Fifo Packet CountTransmit Data Fifo Head Register Rdfpc 02430h R/W Tdfhs 03420h R/W Transmit Data Fifo Tail RegisterTransmit Data Fifo Head Saved Register Tdft 03418h R/W Tdfpc 03430h R/W Transmit Data Fifo Tail Saved RegisterTransmit Data Fifo Packet Count Tdfts 03428h R/W 152. PBM Bit Description Packet Buffer MemoryPBM 10000h 1FFFCh R/W 151. Tdfpc Register Bit Description 370 General Configuration Power Up State Receive Initialization General Initialization and Reset Operation Transmit Initialization Ipgt IPGR1 IPGR2 Fiber Copper 82544GC/EI Signal Ball Name and Function Signal Descriptions Receive Clock Signal InterfaceCarrier Sense Receive Data MII 10/100 Mbps Differences GMII/MII Features not SupportedSignal Functions Signal Function Pin Gmii 1000 Mbps Operations Signal Functions Not Supported Avoiding Gmii Test Modes MAC ConfigurationDirect PHY Indications to MAC CTRL.FD Link Setup CTRL.RFCE PHY Initialization 10/100/1000 Mb/s Copper Media Lanpwrgood Reset Operation 382 Software Developer’s Manual 383 Initialization of Statistics Loopback DiagnosticsFifo State Fifo Data Internal Loopback Testability Bypass Instruction Extest InstructionSAMPLE/PRELOAD Instruction Idcode Instruction 388 Appendix Changes From 82544EI/82544GC New Features EEC Register ChangesTable A-1. Register Changes Register Offset Serial Flash Interface 82540EP/EM Differences Single-Port Functionality No TBI/Internal SerDes Interface4 32-Bit PCI Support

Intel PCI-X, Intel Gigabit Ethernet Controllers manual Receive Interrupt Absolute Delay Timer Radv

Models: Intel Gigabit Ethernet Controllers PCI-X PCI

Figure 3-3. Packet Delay Timer Operation (State Diagram)

3.2.7.1.2Receive Interrupt Absolute Delay Timer (RADV)