Intel PCI-X Receive Data Storage, Receive Descriptor Format, Receive Descriptor Rdesc Layout

Receive and Transmit Description

If manageability is enabled and if RCMCP is enabled then ARP request packets can be directed over the SMBus or processed internally by the ASF controller rather than delivered to host memory (not applicable to the 82544GC/EI or 82541ER.

3.2.2Receive Data Storage

Memory buffers pointed to by descriptors store packet data. Hardware supports seven receive buffer sizes:

•	256 B	•	4096 B
•	512 B	•	8192 B
•	1024 B	•	16384 B

•2048 B

Buffer size is selected by bit settings in the Receive Control register (RCTL.BSIZE & RCTL.BSEX). See Section 13.4.22 for details.

The Ethernet controller places no alignment restrictions on packet buffer addresses. This is desirable in situations where the receive buffer was allocated by higher layers in the networking software stack, as these higher layers may have no knowledge of a specific Ethernet controller’s buffer alignment requirements.

Although alignment is completely unrestricted, it is highly recommended that software allocate receive buffers on at least cache-line boundaries whenever possible.

3.2.3Receive Descriptor Format

A receive descriptor is a data structure that contains the receive data buffer address and fields for hardware to store packet information. Table 3-1lists where the shaded areas indicate fields that are modified by hardware upon packet reception.

Table 3-1. Receive Descriptor (RDESC) Layout

0

8

63	48 47		40 39		32 31		16 15	0
			Buffer Address [63:0]
Special		Errors		Status		Packet Checksum		Length
						(See Note)

82544GC/EI only

0

8

63	48 47		40 39	32 31	16 15	0
			Buffer Address [63:0]
Reserved		Errors		Status	Reserved	Length

Note: The checksum indicated here is the unadjusted “16 bit ones complement” of the packet. A software assist may be required to back out appropriate information prior to sending it to upper software

20 Software Developer’s Manual