Intel Intel Gigabit Ethernet Controllers, PCI-X 11.11 1000 Mbps Operation, Smart Power-Down

PHY Functionality and Features

11.10.1Powerdown via the PHY Register

The PHY can be powered down using the control bit found in PHY register 0d, bit 11. This bit powers down a significant portion of the port but clocks to the register section remain active. This enables the PHY management interface to remain active during power-down. The power-down bit is active high. When the PHY exits software power-down (PHY register 0d, bit 11 = 1b), it re- initializes all analog functions, but retains its previous configuration settings.

11.10.2Smart Power-Down

Smart Power-Down (SPD) is a link-disconnect capability applicable to all power management states, and is intended for mobile applications. Smart powerdown combines a power saving mechanism with the fact that link might disappear and resume.

SPD is enabled by PHY register 20d, bit 5 or by the SPD Enable bit in the EEPROM, and is entered when the PHY detects link lost. Auto-Negotiation must also be enabled. While in the SPD state, the PHY powers down circuits and clocks that are not required for detection of link activity. The PHY is still able to detect link pulses (including parallel detect) and wake up to engage in link negotiation. The PHY does not send link pulses (NLP) while in the SPD state. Register accesses are still possible.

Connecting a member of the family to another system with the SPD feature can lead to link failures if both ports are allowed to enter the SPD state.

11.111000 Mbps Operation

11.11.1Introduction

This section provides an overview of 1000BASE-T functions, followed by discussion and review of the internal functional blocks shown in Figure 11-3.

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