Intel PCI-X, Intel Gigabit Ethernet Controllers manual Software Developer’s Manual 271

Register Descriptions

13.4.7.1.17Extended PHY Specific Control Register 11 EPSCON1 (20d; R/W)

Table 13-39. Extended PHY Specific Control 1 Bit Description1

Field	Bit(s)	Description	Mode	HW Rst	SW Rst
Reserved	1:0	00b	R/W	00b	Retain
Reserved	3	0b	R/W	0b	0
		Reserved. Should be set to 0b.
Reserved	6:4	Changes to this bit are disruptive to the	R/W	110b	Update
		normal operation; any change to this
		register must be followed by software
		reset to take effect.
		Reserved. Should be set to 0b.
Reserved	7	Changes to this bit are disruptive to the	R/W	0b	Update
		normal operation; any change to this
		register must be followed by software
		reset to take effect.
		00b = disable. (10/100 downshift)
		01b = 1x.
		10b = 2x.
Slave downshift		11b = 3x.
	9:8	Changes to this bit are disruptive to the	R/W	01b	Update
counter		normal operation; any change to this
		register must be followed by software
		reset to take effect.
		Bits 11:10 have no effect unless bits 1:0
		are set to their default values.
		00b = 1x.
		01b = 2x.
		10b = 3x.
		11b = 4x.
		Number of times that the PHY attempts
Master downshift		to achieve gigabit link before
	11:10	downshifting to the next speed in Master	R/W	11b	Update
counter		Mode.
		Changes to this bit are disruptive to the
		normal operation; any change to this
		register must be followed by software
		reset to take effect.
		Bits 11:10 have no effect unless bits 1:0
		are set to their default values.
Reserved	12	Reserved. Should be set to 0b.	R/W	0b	0b
Reserved	13	Reserved. Should be set to 0b.	R/W	0b	0b
Reserved	14	Reserved. Should be set to 0b.	R/W	0b	0b
Reserved	15	Reserved. Should be set to 0b.	R/W	0b	0b

1.Extended PHY Specific Control Register - EPSCON for the 82544GC/EI only.

Software Developer’s Manual 271