Intel PCI-X, Intel Gigabit Ethernet Controllers manual 203

Contents

12	Dual Port Characteristics			203
	12.1	Introduction		203
	12.2 Features of Each MAC			203
		12.2.1	PCI/PCI-X interface	203
		12.2.2	MAC Configuration Register Space	205
		12.2.3	SDP, LED, INT# output	205
	12.3	Shared EEPROM		206
		12.3.1	EEPROM Map	206
		12.3.2	EEPROM Arbitration	206
	12.4	Shared FLASH		207
		12.4.1	FLASH Access Contention	207
	12.5	LAN Disable		208
		12.5.1	Overview	208
		12.5.2	Values Sampled on Reset	208
		12.5.3	Multi-Function Advertisement	209
		12.5.4	Interrupt Use	209
		12.5.5	Power Reporting	209
		12.5.6	Summary	210
13	Register Descriptions			211
	13.1	Introduction		211
	13.2	Register Conventions		211
		13.2.1	Memory and I/O Address Decoding	212
		13.2.2	I/O-Mapped Internal Register, Internal Memory, and Flash	213
	13.3 PCI-X Register Access Split			219
	13.4	Main Register Descriptions		220
		13.4.1	Device Control Register	220
		13.4.2	Device Status Register	225
		13.4.3	EEPROM/Flash Control & Data Register	228
		13.4.4	EEPROM Read Register	230
		13.4.5	Flash Access	232
		13.4.6	Extended Device Control Register	233
		13.4.7	MDI Control Register	238
		13.4.8	Flow Control Address Low	279
		13.4.9	Flow Control Address High	279
		13.4.10	Flow Control Type	280
		13.4.11	VLAN Ether Type	280
		13.4.12	Flow Control Transmit Timer Value	281
		13.4.13	Transmit Configuration Word Register	282
		13.4.14	Receive Configuration Word Register	283
		13.4.15	LED Control	285
		13.4.16	Packet Buffer Allocation	288
		13.4.17	Interrupt Cause Read Register	289
		13.4.18	Interrupt Throttling Register	291
		13.4.19	Interrupt Cause Set Register	292
		13.4.20	Interrupt Mask Set/Read Register	293
		13.4.21	Interrupt Mask Clear Register	294
		13.4.22	Receive Control Register	296
		13.4.23	Flow Control Receive Threshold Low	300
		13.4.24	Flow Control Receive Threshold High	301
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