Intel Intel Gigabit Ethernet Controllers, PCI Cache Line Information1, Outstanding Memory Read

PCI Local Bus Interface

Outstanding Memory Read

When the Ethernet controller masters a memory read and is responded to with a split response it waits for the completion of the data as a target. The Ethernet controller allows one outstanding memory read command at any time. The Ethernet controller continues to master posted memory writes and split completions if there are any.

Relaxed Ordering

•The Ethernet controller takes advantage of the relaxed ordering rules in PCI-X. By setting the RO bit for some of its master transactions, the Ethernet controller allows the system to optimize performance in the following cases:

—Relaxed ordering for descriptor and data reads: When the Ethernet controller masters a read transaction its split completion has no relationship with the writes from the CPUs (same direction). It should be allowed to bypass the writes from the CPUs.

—Relaxed ordering for receiving data writes: When the Ethernet controller masters receive data writes it also allows them to bypass each other in the path to system memory because the software does not process this data until their associated descriptor writes are done.

•The Ethernet controller cannot relax ordering for descriptor writes or an MSI write.

No Snoop Setting

The Ethernet controller always clears this bit in all of its master transactions because it cannot guarantee that the memory locations between transaction addresses are not cached in the system.

4.4Cache Line Information1

The cache line size PCI configuration register is programmed by the BIOS and/or OS after a system reset. The value in the cache line size register corresponds to the cache line size that the system supports.

The value programmed into the cache line size register affects the DMA operations of the Ethernet controller. In general, the hardware attempts to fetch descriptors on a cache line basis. It also attempts to write back descriptors when a cache line of descriptors has been filled.

The size of the cache line register also has an effect on the Ethernet controller’s usage of the MWI PCI command, because the use of this command requires that at least a whole cache line of data is written. The memory read commands are also affected as discussed in Section 4.3.2.

In PCI-X mode, the cache line size does not affect the commands used. However it does affect the descriptor transfer. If an unsupported cache line size larger than 128 bytes is programmed, the Ethernet controller acts as if a cache line size of 128 bytes was programmed.

1.Not applicable to the 82547GI/EI.

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